A System on Chip Development of Customizable GA Architecture for Real Parameter Optimization Problem

2016 ◽  
pp. 66-102
Author(s):  
Sumitra Mukhopadhyay ◽  
Soumyadip Das
Keyword(s):  
Evolutionary Algorithm ◽  
Parameter Optimization ◽  
Optimization Problems ◽  
System On Chip ◽  
Real Parameter ◽  
Benchmark Problems ◽  
Modular Architecture ◽  
Field Programmable ◽  
On Chip ◽  
Reconfigurable Device

This chapter presents the design and development of a hardware based architecture of Evolutionary Algorithm for solving both the unimodal and multimodal fixed point real parameter optimization problems. Here a modular architecture has been proposed to provide a tradeoff between real time performance and flexibility and to work as a resource efficient reconfigurable device. The evolutionary algorithm used here is Genetic Algorithm. Prototype implementation of the algorithm has been performed on a system-on-chip field programmable gate array. The notable feature of the architecture is the capability of optimizing a wide class of functions with minimum or no change in the synthesized hardware. The architecture has been tested with ten benchmark problems and it has been observed that for different optimization problems the synthesized target requires maximum of 5% logic slice utilization, 2% of the available block RAMs and 2% of the DSP48 utilization in Xilinx Virtex IV (ML401, XC4VLX25) board.

Evolutionary algorithm characterization in real parameter optimization problems

2013 ◽  
Vol 13 (4) ◽  
pp. 1902-1921 ◽  
Author(s):  
Pilar Caamaño ◽  
Francisco Bellas ◽  
Jose A. Becerra ◽  
Richard J. Duro
Keyword(s):  
Evolutionary Algorithm ◽  
Parameter Optimization ◽  
Optimization Problems ◽  
Real Parameter

A multi-objective evolutionary algorithm based on niche selection in solving irregular Pareto fronts

2021 ◽  
pp. 1-21
Author(s):  
Xin Li ◽  
Xiaoli Li ◽  
Kang Wang
Keyword(s):  
Evolutionary Algorithm ◽  
Optimization Problems ◽  
Optimal Solution ◽  
Benchmark Problems ◽  
Multi Objective Optimization ◽  
Multi Objective ◽  
Environmental Selection ◽  
Optimal Solution Set ◽  
Pareto Fronts

The key characteristic of multi-objective evolutionary algorithm is that it can find a good approximate multi-objective optimal solution set when solving multi-objective optimization problems(MOPs). However, most multi-objective evolutionary algorithms perform well on regular multi-objective optimization problems, but their performance on irregular fronts deteriorates. In order to remedy this issue, this paper studies the existing algorithms and proposes a multi-objective evolutionary based on niche selection to deal with irregular Pareto fronts. In this paper, the crowding degree is calculated by the niche method in the process of selecting parents when the non-dominated solutions converge to the first front, which improves the the quality of offspring solutions and which is beneficial to local search. In addition, niche selection is adopted into the process of environmental selection through considering the number and the location of the individuals in its niche radius, which improve the diversity of population. Finally, experimental results on 23 benchmark problems including MaF and IMOP show that the proposed algorithm exhibits better performance than the compared MOEAs.

Low-Complexity Nonlinear Self-Inverse Permutation for Creating Physically Clone-Resistant Identities

Cryptography ◽  
2020 ◽  
Vol 4 (1) ◽  
pp. 6 ◽  
Author(s):  
Saleh Mulhem ◽  
Ayoub Mars ◽  
Wael Adi
Keyword(s):  
Field Programmable Gate Arrays ◽  
Low Complexity ◽  
System On Chip ◽  
Large Classes ◽  
Physical Unclonable Functions ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Security Levels ◽  
On Chip

New large classes of permutations over ℤ 2 n based on T-Functions as Self-Inverting Permutation Functions (SIPFs) are presented. The presented classes exhibit negligible or low complexity when implemented in emerging FPGA technologies. The target use of such functions is in creating the so called Secret Unknown Ciphers (SUC) to serve as resilient Clone-Resistant structures in smart non-volatile Field Programmable Gate Arrays (FPGA) devices. SUCs concepts were proposed a decade ago as digital consistent alternatives to the conventional analog inconsistent Physical Unclonable Functions PUFs. The proposed permutation classes are designed and optimized particularly to use non-consumed Mathblock cores in programmable System-on-Chip (SoC) FPGA devices. Hardware and software complexities for realizing such structures are optimized and evaluated for a sample expected target FPGA technology. The attained security levels of the resulting SUCs are evaluated and shown to be scalable and usable even for post-quantum crypto systems.

A Computationally Efficient Evolutionary Algorithm for Real-Parameter Optimization

2002 ◽  
Vol 10 (4) ◽  
pp. 371-395 ◽  
Author(s):  
Kalyanmoy Deb ◽  
Ashish Anand ◽  
Dhiraj Joshi
Keyword(s):  
Parameter Optimization ◽  
Optimization Problems ◽  
Research Effort ◽  
Probability Distributions ◽  
Scale Up ◽  
Extensive Study ◽  
Evolution Strategy ◽  
Real Parameter ◽  
Test Problems ◽  
Main Research

Due to increasing interest in solving real-world optimization problems using evolutionary algorithms (EAs), researchers have recently developed a number of real-parameter genetic algorithms (GAs). In these studies, the main research effort is spent on developing an efficient recombination operator. Such recombination operators use probability distributions around the parent solutions to create an offspring. Some operators emphasize solutions at the center of mass of parents and some around the parents. In this paper, we propose a generic parent-centric recombination operator (PCX) and a steady-state, elite-preserving, scalable, and computationally fast population-alteration model (we call the G3 model). The performance of the G3 model with the PCX operator is investigated on three commonly used test problems and is compared with a number of evolutionary and classical optimization algorithms including other real-parameter GAs with the unimodal normal distribution crossover (UNDX) and the simplex crossover (SPX) operators, the correlated self-adaptive evolution strategy, the covariance matrix adaptation evolution strategy (CMA-ES), the differential evolution technique, and the quasi-Newton method. The proposed approach is found to consistently and reliably perform better than all other methods used in the study. A scale-up study with problem sizes up to 500 variables shows a polynomial computational complexity of the proposed approach. This extensive study clearly demonstrates the power of the proposed technique in tackling real-parameter optimization problems.

scholarly journals FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip

2018 ◽  
Vol 7 (2.16) ◽  
pp. 57
Author(s):  
G Prasad Acharya ◽  
M Asha Rani
Keyword(s):  
Computer Aided Design ◽  
Processing System ◽  
System On Chip ◽  
Core System ◽  
Design Cycle ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Aided Design ◽  
Level Parallelism

The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.  

Field-Programmable System-on-Chip for Localization of UGVs in an Indoor iSpace

2014 ◽  
Vol 10 (2) ◽  
pp. 1033-1043 ◽  
Author(s):  
Jorge Rodriguez-Araujo ◽  
Juan J. Rodriguez-Andina ◽  
Jose Farina ◽  
Mo-Yuen Chow
Keyword(s):  
System On Chip ◽  
Field Programmable ◽  
On Chip
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