Asynchronous Hard Real Time Signals Transmission in Embedded Networks

Nowadays in the aerospace industry the router-based onboard embedded networks gradually replacing bus-based networks because they are already not satisfy the aerospace performance requirements. The SpaceWire, GigaSpaceWire and SpaceFibre standards are developing to meet the increasing aerospace requirements. The important requirement for any aerospace embedded onboard network is a transmission of control information and system signals in hard real time. These signals can be synchronous and asynchronous, periodic and aperiodic, with or without acknowledges. The distributed interrupt mechanism is used for asynchronous signal transmission and it is included into the second edition of SpaceWire standard. The Time-code propagation mechanism is used for synchronous signal transmission in SpaceWire. The broadcast messages mechanism is used for transmission of different system signal in SpaceFibre but it does not quite meet the requirements of hard real time. In this paper the authors consider the asynchronous signals transmission with and without acknowledges. The aims of this paper are following: 1) theoretically investigate the distributed interrupt mechanism; 2) to prove its properties; 3) to specify parameters and limitations; 4) to derive the time characteristics. For these purpose the authors developed the analytical model which describe the distributed interrupt propagation mechanism in terms of the graph theory.

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Design of an Intelligent Data Cache with Replacement Policy

International Journal of Embedded and Real-Time Communication Systems ◽

10.4018/ijertcs.2019040106 ◽

2019 ◽

Vol 10 (2) ◽

pp. 87-107

Author(s):

B. Shameedha Begum ◽

N. Ramasubramanian

Keyword(s):

Real Time ◽

Replacement Policy ◽

Data Cache ◽

Cache Performance ◽

Performance Requirements ◽

Novel Approach ◽

Reconfigurable Caches ◽

Real Time Applications ◽

Hard Real Time ◽

Replacement Algorithms

Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.

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