Design of a Field Programmable Gate Array for Swarm Intelligent Controller Based on a Portable Robotic System

Portable robots are considered an important device in many areas such as in medical, space research, emergency situations, applications, etc. The robots complete tasks efficiently and effectively without any human interaction. The most important advantages of portable robots are their small size and very high speed in problem processing with relatively high accuracy and efficiency compared with constant devices. In this paper, the authors discussed the applications of the robot systems based on swarm intelligent controller and field programmable gate array (FPGA). A component-oriented FPGA design platform is proposed for robot system integration because FPGAs are known to be power-efficient hardware platforms. From the results, they found that FPGA and swarm intelligence are very efficient in robotic systems and used in a wide area of applications.

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Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

10.21236/ada492273 ◽

2008 ◽

Cited By ~ 3

Author(s):

Michael Wirthlin ◽

Brent Nelson ◽

Brad Hutchings ◽

Peter Athanas ◽

Shawn Bohner

Keyword(s):

Field Programmable Gate Array ◽

Fpga Design ◽

Design Methodologies ◽

Field Programmable ◽

Gate Array

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High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

International Journal of Sensors Wireless Communications and Control ◽

10.2174/2210327911666210201104151 ◽

2021 ◽

Vol 11 ◽

Author(s):

Ibrahem M. T. Hamidi ◽

Farah S. H. Al-aassi

Keyword(s):

High Throughput ◽

Field Programmable Gate Array ◽

High Speed ◽

Design Tool ◽

Advanced Encryption Standard ◽

Clock Frequency ◽

Advance Encryption Standard ◽

Field Programmable ◽

Internal Component ◽

Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

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Log-Domain Arithmetic for High-Speed Fuzzy Control on a Field-Programmable Gate Array

Soft Computing: State of the Art Theory and Novel Applications - Studies in Fuzziness and Soft Computing ◽

10.1007/978-3-642-34922-5_19 ◽

2013 ◽

pp. 269-287 ◽

Cited By ~ 1

Author(s):

Ali Razib ◽

Scott Dick ◽

Vincent Gaudet

Keyword(s):

Fuzzy Control ◽

Field Programmable Gate Array ◽

High Speed ◽

Field Programmable ◽

Gate Array ◽

Log Domain

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Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Journal of Circuits System and Computers ◽

10.1142/s0218126620501364 ◽

2019 ◽

Vol 29 (09) ◽

pp. 2050136

Author(s):

Yuuki Tanaka ◽

Yuuki Suzuki ◽

Shugang Wei

Keyword(s):

Field Programmable Gate Array ◽

High Speed ◽

Number System ◽

Logic Circuit ◽

Fpga Implementation ◽

Number Representation ◽

Representation System ◽

Representation Systems ◽

Field Programmable ◽

Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

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