Deadlock Free Routing Algorithm for Minimizing Data Packet Transmission in Network on Chip

2012 ◽  
Vol 3 (1) ◽  
pp. 70-81 ◽  
Author(s):  
K. Somasundaram ◽  
Juha Plosila
Keyword(s):  
Communication Networks ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Packet Transmission ◽  
Data Packet ◽  
Destination Node ◽  
Multiple Sources ◽  
Multiple Paths ◽  
On Chip

Network on chip (NoC) has been proposed as a solution for addressing the design challenges of future high performance nanoscale architectures. In NoCs, the traditional routing schemes are routing packets through a single path or multiple paths from one source node to a destination node, minimizing the congestion in the routing architecture. Although these routing algorithms are moderately efficient, they are time dependent. To reduce overall data packet transmission time in the network, the authors consider a network with multiple sources and multiple destinations. Multi-dimensional routing problems appear naturally in several resource allocation problems, communication networks and wireless sensor networks. In this paper, the authors have constructed a deadlock-free multi-dimensional path routing algorithm for minimizing the congestion in NoC.

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

scholarly journals Low latency Path Aware XY-X Routing Algorithm for NoC Architectures

2018 ◽  
Vol 7 (2.7) ◽  
pp. 763
Author(s):  
Venkateswara Rao Musala ◽  
T V Rama Krishna
Keyword(s):  
High Performance ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Destination Node ◽  
Specific Information ◽  
Traffic Patterns ◽  
Traffic Conditions ◽  
Trade Offs ◽  
On Chip

Route specific information with the SoC needs a great deal of wiring, which increases the Resistance & Capacitance (RC) component of the system. Network on Chip (NoC) is utilized as the interface to address the problems in SoC, On-chip interconnection network in NoC has gained more consideration over steadfast wiring and buses, like lower latency, scalability and high performance. Present routing algorithms in NoC is suffered from load balancing at incarnation networks under non-uniform traffic conditions, causes increase the NoC trade-offs (latency and throughput). Adaptive routing is a technique to progress the load balance, but previous adaptive routing techniques used uniform traffic patterns to form the routing decisions. This paper proposes a new approach at non- uniform traffic patterns in channel state and path specific, Path Aware Routing (PAR XY-X) uses a timeout piggybacking for acknowledgement and load shedding to avoid congestion which choose optimistic path calculation unit to connect the destination node without glue logic decisions in routing. PAR XY-X outperforms the Normal XY routing by 20% and 33% with respect to Avg.latency and throughput.

scholarly journals Age-aware Adaptive Routing for Network-on-Chip Routing with Odd-Even Turn Model

2020 ◽  
Vol 4 (2) ◽  
Author(s):  
M. S Saliu ◽  
I. J Umoh ◽  
B.O. Sadiq ◽  
M.O Momoh
Keyword(s):  
Performance Metrics ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Point Of View ◽  
Destination Node ◽  
Traffic Patterns ◽  
Average Latency ◽  
On Chip ◽  
High Degree

This paper presents an age-aware adaptive routing for Odd-Even (OE) turn model. As packets traverse from source to destination node, their paths are defined by a given routing algorithm. For a selected routing algorithm, an efficient arbitration technique is crucial to sharing critical Network-on-Chip resources. Arbitration techniques provide high degree of local fairness from each router point of view. However, there is delay of a packet with a longer path between the source and destination nodes. In order to address this challenge an age-based arbitration technique is hereby proposed for adaptive routing with OE turn model. The age-aware adaptive routing uses an age-based arbitration technique that gives priority to oldest packet. The performance of the developed age-aware adaptive routing was evaluated using different synthetic traffic at different Packet Injection Rates (PIRs). Results were compared with the result obtained on fair arbitration technique for adaptive routing using average latency and throughput as performance metrics. The result indicated that the age-aware adaptive routing has 2.73%, 6.63 %,5.4% and 4.5 % reduction in latency under random, transpose 1 transpose 2 and bit reversal traffic patterns respectively when compared to fair arbitration adaptive routing with OE turn model. For throughput the results indicated that the age-aware adaptive routing with OE turn model has 14.22%, 13%.12% and 19% increase in throughput under random, transpose 1 transpose 2 and bit reversal traffic patterns respectively when compared to fair arbitration adaptive routing with OE turn model.

scholarly journals Bubble NoC – A Low Energy Network-on-Chip with Small Footprint and High Performance

2021 ◽  
Author(s):  
Gunnar Carlstedt ◽  
Mats Rimborg
Keyword(s):  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Transmission Gates ◽  
One Step ◽  
Small Footprint ◽  
On Chip ◽  
Local Connection ◽  
Bidirectional Transmission ◽  
Energy Network

<div>The Bubble NoC is based on simplicity and provides outstanding performance. Flow control is implemented by <i>bubbles</i>, which are inserted between the flits. The logic resembles a traffic situation where a vehicle only moves if the next position is empty. When a flit moves, a bubble is created behind it, and when there is a blocking the bubbles are collapsed as the flits behind are packed together. Even when the Bubble NoC is saturated, it degrades gracefully, and the execution continues.</div><div> Deterministic prerouting is used, with the address stored as markers in a 2 out of 32 code. The routing algorithm shifts the address one step at each hop and turns or finishes when a marker starts the address.</div><div> The physical implementation is a mesh of <i>streets</i> containing duplex links of 38 wires carrying 32-bit payload. Signaling is based on current injection that charges the wires. A switch is placed in a four-way crossing, with a fifth local connection into a street. The switch contains input registers for each approaching street. Straight through traffic is simply passed on, and a diagonal gate is used for turning traffic.</div><div> All switches are bidirectional transmission gates, and the control is distributed as a sidewalk in a few µm of the periphery surrounding the intersection. In a 14 nm technology, the streets are 8 μm wide, the crossing is 17 μm in square, the hop frequency 6.67 GHz and the energy for a datapath 4.1 fJ/bit/hop (150 µm).</div>

scholarly journals A New Efficient and Reliable Dynamically ReconfigurableNetwork-on-Chip

2012 ◽  
Vol 2012 ◽  
pp. 1-16 ◽  
Author(s):  
Cédric Killian ◽  
Camel Tanougast ◽  
Fabrice Monteiro ◽  
Abbas Dandache
Keyword(s):  
Error Detection ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Data Packet ◽  
Reliable Operation ◽  
Detection Mechanism ◽  
Dynamically Reconfigurable ◽  
On Chip ◽  
Online Error Detection

We present a new reliableNetwork-on-Chip(NoC) suitable forDynamically Reconfigurable Multiprocessors on Chipsystems. The proposedNoCis based on routers performing online error detection of routing algorithm and data packet errors. Our work focuses on adaptive routing algorithms which allow to bypass faulty components or processor elements dynamically implemented inside the network. The proposed routing error detection mechanism allows to distinguish routing errors from bypasses of faulty components. The new router architecture is based on additional diagonal state indications and specific logic blocks allowing the reliable operation of theNoC. The main originality in the proposedNoCis that only the permanently faulty parts of the routers are disconnected. Therefore, our approach maintains a high run time throughput in theNoCwithout data packet loss thanks to a self-loopbackmechanism inside each router.

scholarly journals Parallel overloaded CDMA crossbar for network on chip

2019 ◽  
Vol 32 (1) ◽  
pp. 105-118
Author(s):  
Ashok Kumar ◽  
P. Dananjayan
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Large Network ◽  
Network Systems ◽  
Mesh Topology ◽  
Field Programmable ◽  
On Chip ◽  
Code Division Multiple

For high performance of Network on Chip (NoC), Code Division Multiple Access (CDMA) technique is used recently due to its fixed communication delay, reduced area utilisation and low power consumption. The CDMA system uses Walsh based spreading code which improves the bandwidth efficiency. On the contrary, it is not effective when the number of nodes present in the system increases. Overloaded CDMA (OCDMA) is presented for such large network systems. In this paper, OCDMA crossbar is modified and advanced with parallel encoding and decoding operation using orthogonal gold codes for improving the speed of crossbar thereby obtaining high performance in NoC switch. A modified crossbar consisting of extra processing elements is used to enhance the performance of NoC based System on Chip (SoC) system. This work is simulated on Xilinx tool and implemented in Vertex-6 (XC6VLX760) Field Programmable Gate Array (FPGA) device. The proposed work is implemented for four ports, eight ports and sixteen ports with deterministic X-Y routing algorithm in 3 3 NoC design with mesh topology. This NoC switch shows 9.79% improvement in delay and shows 20.76% improvement in power consumption when compared to the existing CDMA NoCs for 8 bit data packet.

scholarly journals Bubble NoC – A Low Energy Network-on-Chip with Small Footprint and High Performance

2021 ◽  
Author(s):  
Gunnar Carlstedt ◽  
Mats Rimborg
Keyword(s):  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Transmission Gates ◽  
One Step ◽  
Small Footprint ◽  
On Chip ◽  
Local Connection ◽  
Bidirectional Transmission ◽  
Energy Network

<div>The Bubble NoC is based on simplicity and provides outstanding performance. Flow control is implemented by <i>bubbles</i>, which are inserted between the flits. The logic resembles a traffic situation where a vehicle only moves if the next position is empty. When a flit moves, a bubble is created behind it, and when there is a blocking the bubbles are collapsed as the flits behind are packed together. Even when the Bubble NoC is saturated, it degrades gracefully, and the execution continues.</div><div> Deterministic prerouting is used, with the address stored as markers in a 2 out of 32 code. The routing algorithm shifts the address one step at each hop and turns or finishes when a marker starts the address.</div><div> The physical implementation is a mesh of <i>streets</i> containing duplex links of 38 wires carrying 32-bit payload. Signaling is based on current injection that charges the wires. A switch is placed in a four-way crossing, with a fifth local connection into a street. The switch contains input registers for each approaching street. Straight through traffic is simply passed on, and a diagonal gate is used for turning traffic.</div><div> All switches are bidirectional transmission gates, and the control is distributed as a sidewalk in a few µm of the periphery surrounding the intersection. In a 14 nm technology, the streets are 8 μm wide, the crossing is 17 μm in square, the hop frequency 6.67 GHz and the energy for a datapath 4.1 fJ/bit/hop (150 µm).</div>

scholarly journals Self-Healing Router Approach for High-Performance Network-on-Chip

2021 ◽  
Vol 2 ◽  
pp. 485-496
Author(s):  
Kasem Khalil ◽  
Omar Eldash ◽  
Ashok Kumar ◽  
Magdy Bayoumi
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Self Healing ◽  
On Chip
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