Two-Dimensional Irregular Packing Algorithm for Strips Cutting Technology in Sheet Steel Industry

2011 ◽  
Vol 130-134 ◽  
pp. 1080-1084
Author(s):  
Miao Xin Pan
Keyword(s):  
Simulated Annealing Algorithm ◽  
Sheet Steel ◽  
Two Dimensional ◽  
Optimal Layout ◽  
Genetic Simulated Annealing Algorithm ◽  
Irregular Shapes ◽  
Packing Algorithm ◽  
Automatic Layout ◽  
Bottom Left ◽  
Annealing Algorithm

This paper proposes a new packing algorithm for strips cutting method in steel plate cutting technology. It remarks the shapes by many horizontal lines. It firstly searches the best sequence and each shape’s angle for packing all shapes by genetic simulated annealing algorithm, and then a new heuristic algorithm which satisfies the practical need of strips cutting technology based on the bottom-left algorithm is used to complete the automatic layout of two dimensional irregular shapes. In the end, satisfactory results of optimal layout are obtained.

scholarly journals Topologically Rectangular Grids in the Parallel Simulation of Semiconductor Devices

VLSI Design ◽  
1998 ◽  
Vol 6 (1-4) ◽  
pp. 91-95 ◽  
Author(s):  
A. Asenov ◽  
A. R. Brown ◽  
S. Roy ◽  
J. R. Barker
Keyword(s):  
Simulated Annealing Algorithm ◽  
Semiconductor Device ◽  
Electronic Device ◽  
Device Simulation ◽  
Power Electronic ◽  
Two Dimensional ◽  
Solution Strategy ◽  
Rectangular Grids ◽  
Annealing Algorithm ◽  
2D And 3D

Topologically rectangular grids offer simplicity and efficiency in the design of parallel semiconductor device simulators tailored for mesh connected MIMD platforms. This paper presents several approaches to the generation of topologically rectangular 2D and 3D grids. The effects of the partitioning of such grids on different processor configurations are studied. A simulated annealing algorithm is used to optimise the partitioning of 2D and 3D grids on two dimensional arrays of processors. Problems related to the discretization, parallel matrix generation and solution strategy are discussed. The use of topologically rectangular grids is illustrated through the example of power electronic device simulation.

scholarly journals Fault Localization Based on Hybrid Genetic Simulated Annealing Algorithm

2021 ◽  
Vol 28 (2) ◽  
pp. 101-109
Keyword(s):  
Simulated Annealing ◽  
Software Testing ◽  
Simulated Annealing Algorithm ◽  
Search Algorithm ◽  
Fault Localization ◽  
Good Effect ◽  
Test Case ◽  
Genetic Simulated Annealing Algorithm ◽  
Starting Point ◽  
Annealing Algorithm

Software testing is an important stage in the software development process, which is the key to ensure software quality and improve software reliability. Software fault localization is the most important part of software testing. In this paper, the fault localization problem is modeled as a combinatorial optimization problem, using the function call path as a starting point. A heuristic search algorithm based on hybrid genetic simulated annealing algorithm is used to locate software defects. Experimental results show that the fault localization method, which combines genetic algorithm, simulated annealing algorithm and function correlation analysis method, has a good effect on single fault localization and multi-fault localization. It greatly reduces the requirement of test case coverage and the burden of the testers, and improves the effect of fault localization.

Sign in / Sign up

Export Citation Format

Share Document