Design and Implementation of Real-Time CNC Interpolation ASIC for Pythagorean Hodograph Curve Based on FPGA

In this paper, a novel architecture of a real-time CNC interpolation ASIC for Pythagorean Hodograph curve based on FPGA is proposed. The ASIC built on a single FPGA chip contains a NikosⅡprocessor core. It uses a two-stage interpolation scheme to reduce the computational burden of PH curve interpolation. Firstly, the 1st-stage interpolation program is operated on the NikosⅡprocessor. The FPGA hardware logic performs the 2nd-stage interpolation and outputs two groups of pulses for the motion control of actuators (two stepper motors)

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Design of Pythagorean Hodograph Curve Interpolator Based on NiosII Embedded Processor and FPGA

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.383-390.6868 ◽

2011 ◽

Vol 383-390 ◽

pp. 6868-6872

Author(s):

Jing Jie Guo ◽

Wei Tang

Keyword(s):

High Speed ◽

Precision Machining ◽

Interpolation Algorithm ◽

Interpolation Scheme ◽

Embedded Processor ◽

Computational Burden ◽

Curve Interpolation ◽

Pythagorean Hodograph ◽

Fpga Chip ◽

Ph Curve

In this paper, a novel architecture of Pythagorean Hodograph (PH) curve interpolator based on Nios Ⅱ embedded processor and FPGA is proposed. The whole interpolator including NiosⅡ processor is built in a single FPGA chip. The interpolator uses a two-stage interpolation scheme to reduce the computational burden of PH curve interpolator. The Nios Ⅱ embedded processor implements 1st-stage interpolation, the FPGA receives the command from the Nios Ⅱ processor and implements 2nd-stage interpolation simultaneously. Therefore, the interpolator can implement the real-time PH curve interpolation algorithm steadily to meet the needs of high-speed and high-precision machining.

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Design and Implementation of Real-time NURBS Interpolator for Motion Control

2007 2nd IEEE Conference on Industrial Electronics and Applications ◽

10.1109/iciea.2007.4318444 ◽

2007 ◽

Cited By ~ 2

Author(s):

C.-Y. Chen ◽

P.-S. Liao ◽

C.-C. Cheng ◽

G.-F. Jong

Keyword(s):

Real Time ◽

Motion Control ◽

Nurbs Interpolator ◽

Design And Implementation

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Quintic Pythagorean-Hodograph Curves Based Trajectory Planning for Delta Robot with a Prescribed Geometrical Constraint

Applied Sciences ◽

10.3390/app9214491 ◽

2019 ◽

Vol 9 (21) ◽

pp. 4491 ◽

Cited By ~ 1

Author(s):

Xu Liang ◽

Tingting Su

Keyword(s):

Real Time ◽

Trajectory Planning ◽

Joint Space ◽

Geometrical Constraint ◽

Planning Approach ◽

Pythagorean Hodograph ◽

Delta Robot ◽

Parameter Dependent ◽

Ph Curve ◽

The Relationship

A new trajectory planning approach on the basis of the quintic Pythagorean–Hodograph (PH) curve is presented and applied to Delta robot for implementing pick-and-place operation (PPO). To satisfy a prescribed geometrical constraint, which indicates the distance between the transition segment curve and right angle of PPO trajectory is no greater than a prescribed value, the quintic PH curve is used to produce a connection segment path for collision avoidance. The relationship between the PH curve and constraint is analyzed, based on which PH curve is calculated simply. Afterwards, the trajectory is planned in different phases with different motion laws, i.e. polynomial motion laws and PH curve parameter-dependent motion laws, to obtain a smooth performance both in Cartesian and joint space. The relationship between the PH curve and constraint is also used to improve the efficiency of calculation, and the trajectory symmetry is used to reduce calculation time by direct symmetric transformation. Thus, real-time performance is improved. The results of simulations and experiments indicate that the approach in this paper can provide smooth motion and meet the real-time requirement under the prescribed geometrical constraint.

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Timeslot Management’s Design and Implementation of AIS Terminal Equipment

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.740.861 ◽

2015 ◽

Vol 740 ◽

pp. 861-865

Author(s):

Ying Jin ◽

Shu Fang Zhang

Keyword(s):

Real Time ◽

Research Topic ◽

Automatic Identification ◽

Identification System ◽

Current Frame ◽

Main Research ◽

Design And Implementation ◽

Fpga Chip ◽

Main Research Topic ◽

Terminal Equipment

Our project team designed and realized an Automatic Identification System (AIS) terminal equipment specifically which is based on an ARM7 chip and compatible with a self-developed FPGA chip. The main research topic is about the timeslot management and implementation in this equipment. I designed a timeslot list in the form of an array, to storage every timeslot state in each channel and current frame real-time, intuitively, and conveniently. When there is a timeslot-occupied or a timeslot-reserved in the equipment, the timeslot list can storage the timeslot state real-time. This timeslot state is defined as whether each timeslot is currently occupied, what action occupied it, how long the timeout is. And manage the timeslot every timeslot by timeout, to realize each timeslot management in A/B channels. When the equipment will select candidate timeslots to send message, it could read the timeslot state by the timeslot number directly to know whether it can send message in this timeslot. Make sure its timeslot reuse, prevent its timeslot collision, and realize the communication real-time and effective.

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