High-Speed and Anti-Interference Parallel Bus Design on Board

2012 ◽  
Vol 182-183 ◽  
pp. 515-519
Author(s):  
Hong Qi Yu ◽  
Sen Liu ◽  
Nan Li ◽  
Meng Wang ◽  
Jin Ling Xing ◽  
...  
Keyword(s):  
Error Correction ◽  
Negative Feedback ◽  
Error Rate ◽  
High Speed ◽  
Low Voltage ◽  
Final Test ◽  
Random Code ◽  
Error Correction Coding ◽  
Differential Transmission ◽  
Synchronous Technology

This paper presents a high-speed and anti-interference parallel bus design on board, which takes a series of measures, including source-synchronous technology, the negative feedback technology, low-voltage differential transmission technology, error correction coding and pseudo-random code technology to improve the environment for parallel communication, increase communication speed, decrease error rate .The final test shows the communication speed has achieved 10 Gbps and the error rate has reduced to 10-7.

Hamming Product Code Based Multiple Bit Error Correction Coding Scheme Using Keyboard Scan Based Decoding for on Chip Interconnects Links

2012 ◽  
Vol 241-244 ◽  
pp. 2457-2461 ◽  
Author(s):  
Murali Maheswari ◽  
Gopalakrishnan Seetharaman
Keyword(s):  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Error Control ◽  
Low Complexity ◽  
Hardware Complexity ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

A Preliminary Study on CSAMT Anti-Jamming Transmitter System

2014 ◽  
Vol 962-965 ◽  
pp. 317-321
Author(s):  
Dang Li ◽  
Jun Lu Wang ◽  
Yong Li ◽  
Jian Hua Li ◽  
Pin Rong Lin
Keyword(s):  
Data Acquisition ◽  
High Voltage ◽  
High Speed ◽  
Low Voltage ◽  
Host Computer ◽  
Good Prospect ◽  
Interference Signal ◽  
Computer Data ◽  
Random Code ◽  
Data Acquisition Card

On the basis of the relevant identification theory of pseudo-random code signal, the signals of CSAMT are divided into three parts according to the frequency of the signal. The signals which are susceptible to 50Hz interference signal and its harmonic components should be set by pseudo-random code way. Others are set by single square waveform way. The Control and signal generation software of the transmitter system is built on the advanced virtual instrument platform, LabVIEW. The hardware of the transmitter system is mainly composed of host computer, data acquisition card, high-speed optocoupler, IGBT driver module and four IGBT switches. The data acquisition card generate PWM signals, the high-speed optocoupler isolates low-voltage part and high-voltage part. IGBT drive module and four IGBT switches constitute high-voltage part. Entire transmitter system is suitable for different environments and research tasks, the transmit frequency are adjustable, and the pseudo-random code signal has strong capability to suppress the interference signals. The control software on host computer is simple and clear. There is good prospect for the use.

Detecting on Forward Error Correction Codes

2013 ◽  
Vol 760-762 ◽  
pp. 96-100
Author(s):  
Zong Li Lai ◽  
Wen Tao Xu
Keyword(s):  
Error Correction ◽  
Significant Role ◽  
Error Rate ◽  
Communication System ◽  
High Speed ◽  
Forward Error Correction ◽  
Error Correction Codes ◽  
Broadband Communication ◽  
Forward Error

Under the development of society, the dissemination of information plays an increasingly significant role. How to achieve the goal of continually reducing the error rate and enhance the quality of communication and construct a highly reliable, efficient and high-speed Broadband Communication System is really a tough task. Here comes the FEC that is one particular type of error correction codes which is introduced to protect the process of data transmitting. In addition to a brief introduction to FEC, this article covers the categories of FEC and their applications along with comparisons and also describes the latest development of these error correction algorithms.

scholarly journals Lightweight hamming product code based multiple bit error correction coding scheme using shared resources for on chip interconnects

2020 ◽  
Vol 9 (5) ◽  
pp. 1979-1989
Author(s):  
Asaad Kadhum Chlaab ◽  
Wameedh Nazar Flayyih ◽  
Fakhrul Zaman Rokhani
Keyword(s):  
Power Consumption ◽  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Total Power ◽  
Shared Resources ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

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