Design of an Images Security System

2010 ◽  
Vol 34-35 ◽  
pp. 1735-1738
Author(s):  
Feng Huang ◽  
Xing Ping Liu

The paper designs an image security system. It includes four parts: keys generation, permutation, diffusion and decryption. Using six decimal numbers as the key, it can get three new keys: key1, key2 and key3 from the origin key in keys generation. The permutation used a new chaotic map to shuffles the image pixels by key1 and key2. The diffusion used the logistic map to flat the histogram of the ciphered image. The key3 is the parameters of the logistic map. The results of simulation show the validity of security system. Analysis shows that it can be used in real-time image encryption applications with high speed.

2018 ◽  
Vol 16 (3) ◽  
pp. 775-790 ◽  
Author(s):  
Fengyong Li ◽  
Haibin Wu ◽  
Gang Zhou ◽  
Weimin Wei

2015 ◽  
Vol 27 (1) ◽  
pp. 12-23 ◽  
Author(s):  
Qingyi Gu ◽  
◽  
Sushil Raut ◽  
Ken-ichi Okumura ◽  
Tadayoshi Aoyama ◽  
...  

<div class=""abs_img""><img src=""[disp_template_path]/JRM/abst-image/00270001/02.jpg"" width=""300"" />Synthesized panoramic images</div> In this paper, we propose a real-time image mosaicing system that uses a high-frame-rate video sequence. Our proposed system can mosaic 512 × 512 color images captured at 500 fps as a single synthesized panoramic image in real time by stitching the images based on their estimated frame-to-frame changes in displacement and orientation. In the system, feature point extraction is accelerated by implementing a parallel processing circuit module for Harris corner detection, and hundreds of selected feature points in the current frame can be simultaneously corresponded with those in their neighbor ranges in the previous frame, assuming that frame-to-frame image displacement becomes smaller in high-speed vision. The efficacy of our system for improved feature-based real-time image mosaicing at 500 fps was verified by implementing it on a field-programmable gate array (FPGA)-based high-speed vision platform and conducting several experiments: (1) capturing an indoor scene using a camera mounted on a fast-moving two-degrees-of-freedom active vision, (2) capturing an outdoor scene using a hand-held camera that was rapidly moved in a periodic fashion by hand. </span>


2014 ◽  
Vol 971-973 ◽  
pp. 1454-1458
Author(s):  
Lei Qu ◽  
Yan Tian ◽  
Jun Liu

For real time target detection, identification and tracking in high frame rates, large field of view images, a real-time image processing system is designed. A TMS320C6678 DSP runs as the chief arithmetic processor of this system and FPGA as the secondary controller. C6678 is compared with the same series C6414 in image compression algorithm test. Experimental results show that the new system has a more effective construct, and higher reliability, and can provide a platform for the new high-speed image processing.


2005 ◽  
Vol 17 (4) ◽  
pp. 420-427 ◽  
Author(s):  
Yoshihiro Watanabe ◽  
◽  
Takashi Komuro ◽  
Shingo Kagami ◽  
Masatoshi Ishikawa

In this paper, we propose a new architecture that can extract information of numerous particles in an image at high-speed. Particle information means various characteristics obtained from image moments. The proposed architecture simultaneously extracts moments of multiple particles in parallel. This parallel extraction enables a significant reduction in the amount of calculation required. In addition, asynchronous operation allows fast processing. We believe that this architecture can obtain more information in real-time even at high frame rates than conventional processing, providing advantages in a wide range of applications, mainly for image measurement. This paper details our proposed architecture and reviews some results of its implementation in FPGA.


2011 ◽  
Vol 467-469 ◽  
pp. 703-708
Author(s):  
Yang Xu ◽  
Ping Li ◽  
Jian Jun Yuan ◽  
Min Xiang

As the real-time image acquiring and processing need to be dealt with high speed, a image acquisition and preprocessing system is discussed in this paper. It is built on FPGA( field programmable gate array ) with pipelined and parallel technology. The configurable macro function modules provided by Altera company achieve the Sobel edge detection algorithm. The real-time display the image after edge detection works properly and The new design method shorten the development cycle.


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