The Characters of Dual Harmonic Frames of Subspaces and Applications in Signal Processing Theory

2013 ◽  
Vol 457-458 ◽  
pp. 731-735
Author(s):  
Yong Yi Huang ◽  
Jian Feng Zhou
Keyword(s):  
Signal Processing ◽  
Information Science ◽  
Digital Signal ◽  
General Purpose ◽  
Decomposition Scheme ◽  
Processing Theory ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Definition Of ◽  
Signal Processors

Digital signal processing is the processing of digitized discrete-time samp-led signals. Processing is done by general-purpose computers or by digital circuits such as ASICs, field-programmable gate arrays or specialized digital signal processors. Information science focuses on understanding problems from the perspective of the stakeholders involved and then applying information and other technologies as needed. The definition of multiple pseudofames for subspaces with integer translation is proposed. The notion of a generalized multiresolution structure (GMS) of is also introduced. The construction of a generalized multiresolution structure of Paley-Wiener subspaces of is investigated. The pyramid decomposition scheme is derived based on a generalized multiresolution structure.

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

An Undergraduate Course and Laboratory in Digital Signal Processing With Field Programmable Gate Arrays

2010 ◽  
Vol 53 (4) ◽  
pp. 638-645 ◽  
Author(s):  
Uwe Meyer-Base ◽  
Alonzo Vera ◽  
Anke Meyer-Base ◽  
Marios S. Pattichis ◽  
Reginald J. Perry
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

scholarly journals BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications

2018 ◽  
Vol 7 (1) ◽  
pp. 1
Author(s):  
M. Parvathi ◽  
N. Vasantha ◽  
K. Satya Prasad
Keyword(s):  
Systems Design ◽  
Digital Signal ◽  
Low Area ◽  
Gate Arrays ◽  
Current Limit ◽  
Maximum Current ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Layout Area ◽  
Signal Processors

One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.

scholarly journals Challenges in Clock Synchronization for On-Site Coding Digital Beamformer

2017 ◽  
Vol 2017 ◽  
pp. 1-8
Author(s):  
Satheesh Bojja Venkatakrishnan ◽  
Elias A. Alwan ◽  
John L. Volakis
Keyword(s):  
Clock Synchronization ◽  
Digital Signal ◽  
Data Converter ◽  
Analog To Digital ◽  
Synchronization Errors ◽  
Digital To Analog Converters ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Signal Synchronization ◽  
Signal Processors

Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.

Sign in / Sign up

Export Citation Format

Share Document