scholarly journals BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications

2018 ◽  
Vol 7 (1) ◽  
pp. 1
Author(s):  
M. Parvathi ◽  
N. Vasantha ◽  
K. Satya Prasad
Keyword(s):  
Systems Design ◽  
Digital Signal ◽  
Low Area ◽  
Gate Arrays ◽  
Current Limit ◽  
Maximum Current ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Layout Area ◽  
Signal Processors

One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.

Designing Discrete and Digital Communication Systems

2021 ◽  
pp. 542-561
Author(s):  
Stevan Berber
Keyword(s):  
Communication Systems ◽  
Digital Signal ◽  
Clear Understanding ◽  
Gate Arrays ◽  
Advantages And Disadvantages ◽  
Shift Keying ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Signal Processors ◽  
The Relationship

In this chapter, the practical aspects of the design of digital discrete communication systems, primarily digital signal processors and field -programmable gate arrays, are analysed. The systems are presented at the level of block schematics, to address the main issues in their design and discuss the advantages and disadvantages of various designs in digital technology. Designs using quadriphase-shift keying and quadrature amplitude modulation are presented separately. The operation of each system is explained in terms of the theoretical structure of the system, which allows a clear understanding of the relationship between the theoretical model of the system and its practical design. The structures of the first, second, and third generation of discrete transceiver designs are presented and discussed.

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

An Undergraduate Course and Laboratory in Digital Signal Processing With Field Programmable Gate Arrays

2010 ◽  
Vol 53 (4) ◽  
pp. 638-645 ◽  
Author(s):  
Uwe Meyer-Base ◽  
Alonzo Vera ◽  
Anke Meyer-Base ◽  
Marios S. Pattichis ◽  
Reginald J. Perry
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

scholarly journals Comparison of reconfigurable structures for flexible word-length multiplication

2008 ◽  
Vol 6 ◽  
pp. 113-118 ◽  
Author(s):  
O. A. Pfänder ◽  
R. Nopper ◽  
H.-J. Pfleiderer ◽  
S. Zhou ◽  
A. Bermak
Keyword(s):  
Power Dissipation ◽  
Word Length ◽  
Digital Signal ◽  
Gate Arrays ◽  
Computing Unit ◽  
Field Programmable ◽  
Embedded Blocks ◽  
Programmable Gate Arrays ◽  
Array Structures ◽  
Reconfigurable Structures

Abstract. Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

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