A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes

2016 ◽  
Vol 833 ◽  
pp. 135-139
Author(s):  
Dayang Nur Salmi Dharmiza Awang Salleh ◽  
Rohana Sapawi

Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

2012 ◽  
Vol 51 ◽  
pp. 04DE07 ◽  
Author(s):  
Dayang Nur Salmi Dharmiza ◽  
Mototada Oturu ◽  
Satoru Tanoi ◽  
Hiroyuki Ito ◽  
Noboru Ishihara ◽  
...  

2018 ◽  
Vol 12 (1) ◽  
pp. 21-33
Author(s):  
Farooq Khaleel ◽  
M. Nadhim Abbas

Background:The plethora of the emerged radio frequency applications makes the frequency spectrum crowded by many applications and hence the ability to detect specific application’s frequency without distortion is a difficult task to achieve.Objective:The goal is to achieve a method to mitigate the highest interferer power in the frequency spectrum in order to eliminate the distortion.Method:This paper presents the application of the proposed tunable 6th-order notch filter on Ultra-Wideband (UWB) Complementary Metal-Oxide-Semiconductor (CMOS) Low Noise Amplifier (LNA) utilising self-forward body bias (SFBB).Results:The proposed filter presents 23.5dBm minimum interferer rejection (IR) and attenuates the interferer signal from -43dBm to -67dBm at frequency 5.17GHz. In addition, the maximum IR is 40dBm and attenuates the interferer signal from -41dBm to -81dBm at frequency 5.785GHz. The proposed filter provides coarse tuning with frequency spacing (10MHz) and soft tuning with frequency spacing (1MHz). The UWB CMOS LNA consumes only 5.22mW from a supply voltage of 1.2V and presents a maximum gain of 14dB at frequency 6.25GHz in the -3dB bandwidth from 4.75GHz to 7.5GHz. In addition, the average noise figure is 3.1dB and the input insertion losses (S11) is less than -12dB along the designed bandwidth. The simulation is performed in Advanced Design System (ADS2016.01) software utilising 180nm Taiwan Semiconductor Manufacturing Company (TSMC) Berkeley Short-channel Insulated Gate Field Effect Model (BSIM3v3) model files.Conclusion:The proposed method achieves high interferer power rejection with both soft and coarse tuning.


2012 ◽  
Vol 51 (4S) ◽  
pp. 04DE07 ◽  
Author(s):  
Dayang Nur Salmi Dharmiza ◽  
Mototada Oturu ◽  
Satoru Tanoi ◽  
Hiroyuki Ito ◽  
Noboru Ishihara ◽  
...  

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