Design of Phase Shift Signal Generator

2010 ◽  
Vol 121-122 ◽  
pp. 745-749
Author(s):  
Guo Hai Xiong ◽  
Xue Jun Gao ◽  
Ling Li Zeng
Keyword(s):  
Phase Shift ◽  
Signal Generator ◽  
Hardware Description Language ◽  
Description Language ◽  
Design Time ◽  
Dsp Builder ◽  
Digitally Controlled ◽  
Hardware Description ◽  
Waveform Simulation ◽  
Setting Parameters

A phase shift signal generator which has high precision and whose phase can be easily and digitally controlled is designed through utilizing DDS technology. A method which can replace complicated hardware description language programming through calling modules and setting parameters is proposed. The designed phase shift signal generator passes waveform simulation under Simulink and SignalTap Ⅱcertification, and the results obtained on the FPGA board are correct. The DSP Builder is utilized to design the phase shift signal generator, which reduces the difficulty of the design and shortens the design time.

The Design of Digital Filter Based on DSP Builder

2014 ◽  
Vol 602-605 ◽  
pp. 2641-2644
Author(s):  
Xiao Li Hu ◽  
Li Ding ◽  
Zhi Gang Zhang
Keyword(s):  
Digital Filter ◽  
Hardware Description Language ◽  
Description Language ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Paper Model ◽  
Dsp Builder ◽  
Quartus Ii ◽  
Low Pass ◽  
Hardware Description

This paper model digital FIR low-pass by using the Toolbox of the DSP Builder in MATLAB and convert to VHDL hardware description language, compile and simulation through QUARTUS II software automatically, download and verified by EPF10K20RC208-4.The design combine MATLAB software with FPGA hardware organic ally and completes the transplant of the FIR low-pass filter.

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

2017 ◽  
Vol 26 (09) ◽  
pp. 1750135 ◽  
Author(s):  
Ranjan Kumar Barik ◽  
Manoranjan Pradhan ◽  
Rutuparna Panda
Keyword(s):  
Final Stage ◽  
Hardware Description Language ◽  
Binary Representation ◽  
Description Language ◽  
Power Product ◽  
Efficient Conversion ◽  
Look Ahead ◽  
Hardware Description ◽  
Sign Extension ◽  
Cadence Tool

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

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