FPGA Based Implementation of Semi-Fragile Watermarking Algorithm
2012 ◽
Vol 532-533
◽
pp. 1419-1423
Keyword(s):
This paper presents an FPGA implementation of a semi-fragile watermarking-based algorithm for a digital camera. The architecture of digital authentication camera is discussed and a semi-fragile watermarking algorithm based the invariant property of DCT coefficients quantization is designed which can survive a certain amount of compression. The components of a digital camera and the watermarking algorithm are described in Verilog HDL and implemented on the DE2-70 board. The results shown that the hardware implementation can provide real time performance and resist off-line attacks compare with the software-assisted solution.
Keyword(s):
2011 ◽
Vol 57
(2)
◽
pp. 664-672
◽
Keyword(s):
Keyword(s):
2014 ◽
Vol 7
(4)
◽
pp. 694
Keyword(s):
2020 ◽
Vol E103.A
(12)
◽
pp. 1472-1480
Keyword(s):
2014 ◽
Vol 39
(5)
◽
pp. 658-663
◽
Simulation research on real-time performance of CAN bus based on distributed dynamic prior-ity queue
2011 ◽
Vol 25
(7)
◽
pp. 591-596
◽