Four Bit Priority Resolution Network Using Current Mode Winner Take all Circuit

2014 ◽  
Vol 889-890 ◽  
pp. 886-889
Author(s):  
Wen Qin Cao ◽  
Hai Yan Zhu ◽  
Guo Ping Tu
Keyword(s):  
Current Mode ◽  
Cmos Process ◽  
Process Technology ◽  
Output Stage ◽  
New Approach ◽  
Input Stage ◽  
Load Resistor ◽  
Winner Takes All ◽  
Winner Take All ◽  
Take All

This paper presents a new approach for making a four bit priority resolution circuit using current mode winner Take all (WTA) analog computation cells, the winner-takes-all circuit is employed to evaluate the highest input among a set of competing inputs and inhibit the others. This circuit consists of an input stage, a current mode Lazzaros WTA circuit and an output stage consisting of current mirror and load resistor. This circuit is compact, consisting of a total of 28 transistors including the input stage, and a good linearity is observed in response. Simulation of proposed circuit is performed on cadence virtuoso software in 0.18 μm CMOS process technology.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Winner-Take-All Class AB Input Stage

2005 ◽  
Vol 46 (2) ◽  
pp. 149-152 ◽  
Author(s):  
Sushmita Baswa ◽  
Antonio J. López Martín ◽  
Jaime Ramirez-Angulo ◽  
Ramon G. Carvajal
Keyword(s):  
Input Stage ◽  
Class Ab ◽  
Winner Take All ◽  
Take All

Mixed-Mode Universal Biquadratic Filter with No Need of Matching Conditions

2016 ◽  
Vol 25 (09) ◽  
pp. 1650106 ◽  
Author(s):  
Chen-Nong Lee
Keyword(s):  
Mixed Mode ◽  
Current Mode ◽  
Cmos Process ◽  
Current Conveyors ◽  
Process Technology ◽  
Matching Conditions ◽  
Fully Differential ◽  
Control Factors ◽  
Biquadratic Filter ◽  
Component Matching

None of the previously reported mixed-mode universal filters can achieve the following important advantage: no need of component matching conditions. This paper presents a new mixed-mode (including voltage, current, transadmittance, and transimpedance modes) universal biquadratic filter with no need of matching conditions (including no need of component matching and no need of input matching conditions). The proposed filter structure with nine outputs employs two plus-type fully differential current conveyors (P-type FDCCIIs), two grounded capacitors, four grounded resistors and one floating/grounded resistor, which can realize voltage, current, transadmittance, and transimpedance modes universal filtering responses (lowpass, highpass, bandpass, notch, and allpass) from the same topology without matching conditions. Moreover, the proposed circuit still offers many important advantages: the employment of two grounded capacitors, the simultaneous realizations of a lot of filtering functions, using only grounded resistors as the control factors of all filter parameters and gains, having controllable gains in current and transimpedance modes without disturbing filter parameters [Formula: see text], [Formula: see text]/Q, and Q, cascadably connecting the former voltage-mode (VM) stage and the latter current-mode (CM) stage, no capacitors bringing extra poles degrading high-frequency performance, and low active and passive sensitivity performances. H-spice simulations with TSMC 0.18[Formula: see text][Formula: see text]m 1[Formula: see text]P6M CMOS process technology validate theoretical predictions.

Sign in / Sign up

Export Citation Format

Share Document