A High Efficient Baseband GNSS Signal Narrow Band Anti-Jamming Approach in Frequency Domain

2014 ◽  
Vol 926-930 ◽  
pp. 1857-1860
Author(s):  
Zhou Zheng ◽  
Meng Yuan Li ◽  
Wei Jiang Wang
Keyword(s):  
Signal Processing ◽  
Frequency Domain ◽  
Narrow Band ◽  
Low Frequency ◽  
Frequency Resolution ◽  
Interference Rejection ◽  
High Efficient ◽  
Digital Down Conversion ◽  
Down Conversion ◽  
Low Rate

In order to reduce the burden of the calculation and the low frequency resolution of the tradition GNSS signal intermediate narrow band anti-jamming method, it introduces a high efficient approach of narrow band interference rejection based on baseband GNSS signal processing. After digital down conversion to baseband and down sampling to a low rate, the interference is removed in frequency domain. According to the theoretical analysis and simulation, it claims that the method can reduce the calculation and increase the detection resolution in frequency domain which will realize a high efficient interference rejection.

scholarly journals Frequency Domain based Digital Down Conversion Architecture for Software Defined Radio and Cognitive Radio

2018 ◽  
Vol 7 (2.16) ◽  
pp. 88 ◽  
Author(s):  
Latha Sahukar ◽  
Dr M. Madhavi Latha
Keyword(s):  
Cognitive Radio ◽  
Frequency Domain ◽  
Software Defined Radio ◽  
Sampling Rate ◽  
Complex Multiplication ◽  
Clock Rate ◽  
Direct Rotation ◽  
Digital Down Conversion ◽  
Frequency Domain Filtering ◽  
Down Conversion

This paper presents a sampling rate digital down converter that is totally based on frequency domain processing. The proposed DDC is targeted for Software Defined Radio and Cognitive Radio architectures. The proposed architecture is based on replacement of the complex multiplication with direct rotation of the spectrum. Different aspects of frequency domain filtering are also discussed. The Xilinx Virtex-6 family FPGA, XC6VLX240T is used for the implementation and synthesis of the proposed FFT-IFFT based architecture. The overlapping in time domain at the output of the IFFT block is avoided using overlap and add method. In terms area, highly optimized implementation is observed in the proposed architecture when compared to the conventional DDC. The synthesis results have shown that the developed core works at a maximum clock rate of 250 MHz and at the same time  occupies  only 10% of the slices of  FPGA. 

Frequency domain of weakly translation invariant frame MRAs

2021 ◽  
Author(s):  
Zhihua Zhang
Keyword(s):  
Signal Processing ◽  
Data Analysis ◽  
Frequency Domain ◽  
Scaling Function ◽  
Narrow Band ◽  
Scaling Functions ◽  
Translation Invariant ◽  
Frequency Domains ◽  
Band Signal

Frequency domain of bandlimited frame multiresolution analyses (MRAs) plays a key role when derived framelets are applied into narrow-band signal processing and data analysis. In this study, we give a characterization of frequency domain of weakly translation invariant frame scaling functions [Formula: see text] with frequency domain [Formula: see text]. Based on it, we further study convex and ball-shaped frequency domains. If frequency domain of bandlimited frame scaling function [Formula: see text] is convex and completely symmetric about the origin, then it must be weakly invariant and [Formula: see text]. If [Formula: see text] has a ball-shaped frequency domain, the ball radius must be bounded by [Formula: see text]. These frequency domain characters are owned uniquely by frame scaling functions and not by orthogonal scaling functions.

MATLAB Simulation of DBPM Digital Down Conversion

2013 ◽  
Vol 333-335 ◽  
pp. 680-683
Author(s):  
Xu Dong Sun ◽  
Yong Bin Leng
Keyword(s):  
Signal Processing ◽  
Software Defined Radio ◽  
Data Flow ◽  
Flow Diagram ◽  
Critical Parameters ◽  
Signal Source ◽  
Matlab Simulation ◽  
Data Flow Diagram ◽  
Digital Down Conversion ◽  
Down Conversion

A software defined radio architecture algorithm is applied to Digital BPM processor for its signal processing. The algorithm is evaluated in MATLAB with data acquired from the instrument with a commercial signal source as input.The data flow diagram of the algorithm is shown and explained, critical parameters of the filters are displayed and the results are shown which testify the feasibility of the method.

scholarly journals A phase-locked loop using ESO-based loop filter for grid-connected converter: performance analysis

2021 ◽  
Author(s):  
Baoling Guo ◽  
Seddik Bacha ◽  
Mazen Alamir ◽  
Julien Pouget
Keyword(s):  
Performance Analysis ◽  
Frequency Domain ◽  
Low Frequency ◽  
Experimental Tests ◽  
Frequency Measurement ◽  
Phase Locked Loop ◽  
Frequency Domain Analysis ◽  
Loop Filter ◽  
Control Stability ◽  
Unbalanced Grid

AbstractAn extended state observer (ESO)-based loop filter is designed for the phase-locked loop (PLL) involved in a disturbed grid-connected converter (GcC). This ESO-based design enhances the performances and robustness of the PLL, and, therefore, improves control performances of the disturbed GcCs. Besides, the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions. The unbalanced grid is particularly taken into account for the performance analysis. A tuning approach based on the well-designed PI controller is discussed, which results in a fair comparison with conventional PI-type PLLs. The frequency domain properties are quantitatively analysed with respect to the control stability and the noises rejection. The frequency domain analysis and simulation results suggest that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency, while have better ability to attenuate high-frequency measurement noises. The phase margin decreases slightly, but remains acceptable. Finally, experimental tests are conducted with a hybrid power hardware-in-the-loop benchmark, in which balanced/unbalanced cases are both explored. The obtained results prove the effectiveness of ESO-based PLLs when applied to the disturbed GcC.

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