Implementation Aware Hardware Trojan Trigger

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.933.482 ◽

2014 ◽

Vol 933 ◽

pp. 482-486

Author(s):

Masaya Yoshikawa ◽

Yusuke Mori ◽

Takeshi Kumaki

Keyword(s):

Manufacturing Process ◽

Field Programmable Gate Array ◽

Large Scale ◽

Hardware Trojan ◽

Confidential Information ◽

Hardware Trojans ◽

Field Programmable ◽

Gate Array

Recently, the threat of hardware Trojans has garnered attention. Hardware Trojans are malicious circuits that are incorporated into large-scale integrations (LSIs) during the manufacturing process. When predetermined conditions specified by an attacker are satisfied, the hardware Trojan is triggered and performs subversive activities without the LSI users even being aware of these activities. In previous studies, a hardware Trojan was incorporated into a cryptographic circuit to estimate confidential information. However, Trojan triggers have seldom been studied. The present study develops several new Trojan triggers and each of them is embedded in a field-programmable gate array (FPGA). Subsequently, the ease of detection of each trigger is verified from the standpoint of area.

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Very large‐scale integration architecture for video stabilisation and implementation on a field programmable gate array‐based autonomous vehicle

IET Computer Vision ◽

10.1049/iet-cvi.2014.0120 ◽

2015 ◽

Vol 9 (4) ◽

pp. 559-569 ◽

Cited By ~ 3

Author(s):

Tahiyah Nou‐Shene ◽

Vikramkumar Pudi ◽

K. Sridharan ◽

Vineetha Thomas ◽

J. Arthi

Keyword(s):

Field Programmable Gate Array ◽

Large Scale ◽

Autonomous Vehicle ◽

Very Large Scale Integration ◽

Integration Architecture ◽

Field Programmable ◽

Large Scale Integration ◽

Gate Array ◽

Scale Integration

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AN EFFECTIVE APPROACH OF BILATERAL FILTER IMPLEMENTATION IN SPARTAN-3 FIELD PROGRAMMABLE GATE ARRAY

Graduate Research in Engineering and Technology ◽

10.47893/gret.2013.1005 ◽

2013 ◽

pp. 17-20

Author(s):

P. KARTHIKEYAN ◽

M. GAUTHAM ◽

R. RAMAKRISHNAN ◽

A. MOOKKAIYA

Keyword(s):

Field Programmable Gate Array ◽

High Performance ◽

Large Scale ◽

Vlsi Architecture ◽

Cost Effective ◽

Bilateral Filter ◽

Bilateral Filtering ◽

High Resource ◽

Field Programmable ◽

Gate Array

This paper presents the Field Programmable Gate Array (FPGA) implementation of Bilateral Filter, in order to achieve high performance and low power consumption. Bilateral filtering is a technique to smooth images while preserving edges by means of a nonlinear combination of nearby image values. This method is nonlinear, local, and simple. We give an idea that bilateral filtering can be accelerated by bilateral grid scheme that enables fast edge-aware image processing. Nowadays, most of the applications require real time hardware systems with large computing potentiality for which fast and dedicated Very Large Scale Integration (VLSI) architecture appears to be the best possible solution. While it ensures high resource utilization, that too in cost effective platforms like FPGA, designing such architecture does offers some flexibilities like speeding up the computation by adapting more pipelined structures and parallel processing possibilities of reduced memory consumptions. Here we have developed an effective approach of bilateral filter implementation in Spartan-3 FPGA.

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Research on Hex Programmable Interconnect Points Test in Island-Style FPGA

Electronics ◽

10.3390/electronics9122177 ◽

2020 ◽

Vol 9 (12) ◽

pp. 2177

Author(s):

Fan Zhang ◽

Chenguang Guo ◽

Shifeng Zhang ◽

Lei Chen ◽

Xuewu Li ◽

...

Keyword(s):

Coordinate System ◽

Manufacturing Process ◽

Field Programmable Gate Array ◽

Fault Coverage ◽

Test Structure ◽

Two Dimensional ◽

Oblique Direction ◽

Field Programmable ◽

Gate Array

With the decreasing size of manufacturing process, the scale of island-style field programmable gate array (FPGA) becomes larger, which leads to the increasing complexity of FPGA routing resources, especially hex programmable interconnect points (PIPs). Hex PIPs which span six tiles of the island-style FPGA have complex interconnect rules. Accordingly, research on complete hex PIPs test is rarely involved in the study of routing resources test. Therefore, this paper analyzes the hex PIPs architecture of the island-style FPGA, summarizes the interconnect rules of the hex PIPs mathematically in a two-dimensional coordinate system, and presents two proper test algorithms at the same time. The hex PIPs are divided into three directions, that is, horizontal, vertical, and oblique. According to the proposed coordinate equations, a cycle test structure in the horizontal and vertical directions and a test structure with partial-cascade patterns in the oblique direction are designed respectively. It is concluded that the proposed methods can achieve 100% fault coverage for the hex PIPs test in all directions, and the configuration number for hex lines test with the same methods is significantly decreased than previous researches.

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