Research and Analysis of Design and Optimization of Magnetic Memory Material Cache Based on STT-MRAM

2019 ◽  
Vol 815 ◽  
pp. 28-34
Author(s):  
Tian Liu ◽  
Wei Zhang ◽  
Tao Xu ◽  
Guan Wang

This paper proposes a cache replacement algorithm based on STT-MRAM magnetic memory, which aims to make the material system based on STT-MRAM magnetic memory better used. The algorithm replaces the data blocks in the cache by considering the position of the STT-MRAM magnetic memory head and the hardware characteristics of the STT-MRAM magnetic memory. This method will be different from the traditional magnetic memory-based common cache replacement algorithm. Traditional replacement algorithms are generally designed with only the algorithm to improve the cache, and the hardware characteristics of the storage device are ignored. This method can improve the material characteristics of the STT-MRAM magnetic memory by improving the cache life and efficiency.

Author(s):  
A. V. Vishnekov ◽  
E. M. Ivanova

The paper investigates the issues of increasing the performance of computing systems by improving the efficiency of cache memory, analyzes the efficiency indicators of replacement algorithms. We show the necessity of creation of automated or automatic means for cache memory tuning in the current conditions of program code execution, namely a dynamic cache replacement algorithms control by replacement of the current replacement algorithm by more effective one in current computation conditions. Methods development for caching policy control based on the program type definition: cyclic, sequential, locally-point, mixed. We suggest the procedure for selecting an effective replacement algorithm by support decision-making methods based on the current statistics of caching parameters. The paper gives the analysis of existing cache replacement algorithms. We propose a decision-making procedure for selecting an effective cache replacement algorithm based on the methods of ranking alternatives, preferences and hierarchy analysis. The critical number of cache hits, the average time of data query execution, the average cache latency are selected as indicators of initiation for the swapping procedure for the current replacement algorithm. The main advantage of the proposed approach is its universality. This approach assumes an adaptive decision-making procedure for the effective replacement algorithm selecting. The procedure allows the criteria variability for evaluating the replacement algorithms, its’ efficiency, and their preference for different types of program code. The dynamic swapping of the replacement algorithm with a more efficient one during the program execution improves the performance of the computer system.


2007 ◽  
Vol 08 (02) ◽  
pp. 147-162 ◽  
Author(s):  
JAMES Z. WANG ◽  
VIPUL BHULAWALA

In this paper, we design and implement a P2P cooperative proxy caching system based on a novel P2P cooperative proxy caching scheme. To effectively locate the cached web documents, a TTL-based routing protocol is proposed to manage the query and response messages in the P2P cooperative proxy cache system. Furthermore, we design a predict query-route algorithm to improve the TTL-based routing protocol by adding extra information in the query message packets. To select a suitable cache replacement algorithm for the P2P cooperative proxy cache system, three different cache replacement algorithms, LRU, LFU and SIZE, are evaluated using web trace based performance studies on the implemented P2P cooperative proxy cache system. The experimental results show that LRU is an overall better cache replacement algorithm for the P2P proxy cache system although SIZE based cache replacement approach produces slightly better cache hit ratio when cache size is very small. The performance studies also demonstrate that the proposed message routing protocols significantly improve the performance of the P2P cooperative proxy cache system, in terms of cache hit ratio, byte hit ratio, user request latency, and the number of query messages generated in the proxy cache system, compared to the flooding based message routing protocol.


2021 ◽  
Vol 17 (2) ◽  
pp. 1-45
Author(s):  
Cheng Pan ◽  
Xiaolin Wang ◽  
Yingwei Luo ◽  
Zhenlin Wang

Due to large data volume and low latency requirements of modern web services, the use of an in-memory key-value (KV) cache often becomes an inevitable choice (e.g., Redis and Memcached). The in-memory cache holds hot data, reduces request latency, and alleviates the load on background databases. Inheriting from the traditional hardware cache design, many existing KV cache systems still use recency-based cache replacement algorithms, e.g., least recently used or its approximations. However, the diversity of miss penalty distinguishes a KV cache from a hardware cache. Inadequate consideration of penalty can substantially compromise space utilization and request service time. KV accesses also demonstrate locality, which needs to be coordinated with miss penalty to guide cache management. In this article, we first discuss how to enhance the existing cache model, the Average Eviction Time model, so that it can adapt to modeling a KV cache. After that, we apply the model to Redis and propose pRedis, Penalty- and Locality-aware Memory Allocation in Redis, which synthesizes data locality and miss penalty, in a quantitative manner, to guide memory allocation and replacement in Redis. At the same time, we also explore the diurnal behavior of a KV store and exploit long-term reuse. We replace the original passive eviction mechanism with an automatic dump/load mechanism, to smooth the transition between access peaks and valleys. Our evaluation shows that pRedis effectively reduces the average and tail access latency with minimal time and space overhead. For both real-world and synthetic workloads, our approach delivers an average of 14.0%∼52.3% latency reduction over a state-of-the-art penalty-aware cache management scheme, Hyperbolic Caching (HC), and shows more quantitative predictability of performance. Moreover, we can obtain even lower average latency (1.1%∼5.5%) when dynamically switching policies between pRedis and HC.


2019 ◽  
Vol 9 (1) ◽  
Author(s):  
Jodi M. Iwata-Harms ◽  
Guenole Jan ◽  
Santiago Serrano-Guisan ◽  
Luc Thomas ◽  
Huanlong Liu ◽  
...  

AbstractPerpendicular magnetic anisotropy (PMA) ferromagnetic CoFeB with dual MgO interfaces is an attractive material system for realizing magnetic memory applications that require highly efficient, high speed current-induced magnetic switching. Using this structure, a sub-nanometer CoFeB layer has the potential to simultaneously exhibit efficient, high speed switching in accordance with the conservation of spin angular momentum, and high thermal stability owing to the enhanced interfacial PMA that arises from the two CoFeB-MgO interfaces. However, the difficulty in attaining PMA in ultrathin CoFeB layers has imposed the use of thicker CoFeB layers which are incompatible with high speed requirements. In this work, we succeeded in depositing a functional CoFeB layer as thin as five monolayers between two MgO interfaces using magnetron sputtering. Remarkably, the insertion of Mg within the CoFeB gave rise to an ultrathin CoFeB layer with large anisotropy, high saturation magnetization, and good annealing stability to temperatures upwards of 400 °C. When combined with a low resistance-area product MgO tunnel barrier, ultrathin CoFeB magnetic tunnel junctions (MTJs) demonstrate switching voltages below 500 mV at speeds as fast as 1 ns in 30 nm devices, thus opening a new realm of high speed and highly efficient nonvolatile memory applications.


2006 ◽  
Vol 11 (5) ◽  
pp. 1141-1146
Author(s):  
Zhu Jiang ◽  
Shen Qingguo ◽  
Tang Tang ◽  
Li Yongqiang

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