DYNAMIC CONTROL METHODS OF CACHE LINES REPLACEMENT POLICY

2020 ◽  
pp. 49-56
Author(s):  
A. V. Vishnekov ◽  
E. M. Ivanova
Keyword(s):  
Decision Making ◽  
Dynamic Control ◽  
Replacement Policy ◽  
Cache Memory ◽  
Cache Replacement ◽  
Program Code ◽  
Methods Development ◽  
Replacement Algorithm ◽  
Type Definition ◽  
Replacement Algorithms

The paper investigates the issues of increasing the performance of computing systems by improving the efficiency of cache memory, analyzes the efficiency indicators of replacement algorithms. We show the necessity of creation of automated or automatic means for cache memory tuning in the current conditions of program code execution, namely a dynamic cache replacement algorithms control by replacement of the current replacement algorithm by more effective one in current computation conditions. Methods development for caching policy control based on the program type definition: cyclic, sequential, locally-point, mixed. We suggest the procedure for selecting an effective replacement algorithm by support decision-making methods based on the current statistics of caching parameters. The paper gives the analysis of existing cache replacement algorithms. We propose a decision-making procedure for selecting an effective cache replacement algorithm based on the methods of ranking alternatives, preferences and hierarchy analysis. The critical number of cache hits, the average time of data query execution, the average cache latency are selected as indicators of initiation for the swapping procedure for the current replacement algorithm. The main advantage of the proposed approach is its universality. This approach assumes an adaptive decision-making procedure for the effective replacement algorithm selecting. The procedure allows the criteria variability for evaluating the replacement algorithms, its’ efficiency, and their preference for different types of program code. The dynamic swapping of the replacement algorithm with a more efficient one during the program execution improves the performance of the computer system.

IMPROVING peLIFO CACHE REPLACEMENT POLICY: HARDWARE REDUCTION AND THREAD-AWARE EXTENSION

2014 ◽  
Vol 23 (04) ◽  
pp. 1450046
Author(s):  
ENRIQUE SEDANO ◽  
SILVIO SEPULVEDA ◽  
FERNANDO CASTRO ◽  
DANIEL CHAVER ◽  
RODRIGO GONZALEZ-ALBERQUILLA ◽  
...  
Keyword(s):  
New York ◽  
Replacement Policy ◽  
Cache Replacement ◽  
Dynamic Information ◽  
Processor Performance ◽  
Replacement Algorithm ◽  
L2 Cache ◽  
Cache Efficiency ◽  
Performance Penalty

Studying blocks behavior during their lifetime in cache can provide useful information to reduce the miss rate and therefore improve processor performance. According to this rationale, the peLIFO replacement algorithm [M. Chaudhuri, Proc. Micro'09, New York, 12–16 December, 2009, pp. 401–412], which learns dynamically the number of cache ways required to satisfy short-term reuses preserving the remaining ways for long-term reuses, has been recently proposed. In this paper, we propose several changes to the original peLIFO policy in order to reduce the implementation complexity involved, and we extend the algorithm to a shared-cache environment considering dynamic information about threads behavior to improve cache efficiency. Experimental results confirm that our simplification techniques reduce the required hardware with a negligible performance penalty, while the best of our thread-aware extension proposals reduces average CPI by 8.7% and 15.2% on average compared to the original peLIFO and LRU respectively for a set of 43 multi-programmed workloads on an 8 MB 16-way set associative shared L2 cache.

scholarly journals Coherence State Awareness in Way-Replacement Algorithms for Multicore Processors

2019 ◽  
Author(s):  
Matheus Souza ◽  
Henrique Cota Freitas ◽  
Frédéric Pétrot
Keyword(s):  
Multicore Processors ◽  
Great Depth ◽  
General Purpose ◽  
Replacement Policy ◽  
Program Execution ◽  
Cache Replacement ◽  
Performance Impact ◽  
Account Information ◽  
Replacement Algorithms ◽  
Selection Algorithms

Due to their performance impact on program execution, cache replacement policies in set-associative caches have been studied in great depth. Currently, most general-purpose processors are multi-core, and among the very large corpus of research, and much to our surprise, we could not find any replacement policy that does actually take into account information relative to the sharing state of a cache way. Therefore, in this paper we propose to add, as a complement to the classical time-based related way-selection algorithms, an information relative to the sharing state and number of sharers of the ways. We propose several approaches to take this information into account, and our simulations show that LRU-based replacement policies can be slightly improved by them. Also, a much simpler policy, MRU, can be improved by our strategies, presenting up to 3.5× more IPC than baseline, and up to 82% less cache misses.

Research and Analysis of Design and Optimization of Magnetic Memory Material Cache Based on STT-MRAM

2019 ◽  
Vol 815 ◽  
pp. 28-34
Author(s):  
Tian Liu ◽  
Wei Zhang ◽  
Tao Xu ◽  
Guan Wang
Keyword(s):  
Storage Device ◽  
Magnetic Memory ◽  
Cache Replacement ◽  
Material System ◽  
Design And Optimization ◽  
Replacement Algorithm ◽  
Memory Material ◽  
Material Characteristics ◽  
Replacement Algorithms

This paper proposes a cache replacement algorithm based on STT-MRAM magnetic memory, which aims to make the material system based on STT-MRAM magnetic memory better used. The algorithm replaces the data blocks in the cache by considering the position of the STT-MRAM magnetic memory head and the hardware characteristics of the STT-MRAM magnetic memory. This method will be different from the traditional magnetic memory-based common cache replacement algorithm. Traditional replacement algorithms are generally designed with only the algorithm to improve the cache, and the hardware characteristics of the storage device are ignored. This method can improve the material characteristics of the STT-MRAM magnetic memory by improving the cache life and efficiency.

scholarly journals DESIGN AND IMPLEMENTATION OF A P2P COOPERATIVE PROXY CACHE SYSTEM

2007 ◽  
Vol 08 (02) ◽  
pp. 147-162 ◽  
Author(s):  
JAMES Z. WANG ◽  
VIPUL BHULAWALA
Keyword(s):  
Performance Studies ◽  
Routing Protocol ◽  
Cache Replacement ◽  
Proxy Caching ◽  
Message Routing ◽  
Proxy Cache ◽  
Replacement Algorithm ◽  
Cache Hit Ratio ◽  
Replacement Algorithms ◽  
Cache System

In this paper, we design and implement a P2P cooperative proxy caching system based on a novel P2P cooperative proxy caching scheme. To effectively locate the cached web documents, a TTL-based routing protocol is proposed to manage the query and response messages in the P2P cooperative proxy cache system. Furthermore, we design a predict query-route algorithm to improve the TTL-based routing protocol by adding extra information in the query message packets. To select a suitable cache replacement algorithm for the P2P cooperative proxy cache system, three different cache replacement algorithms, LRU, LFU and SIZE, are evaluated using web trace based performance studies on the implemented P2P cooperative proxy cache system. The experimental results show that LRU is an overall better cache replacement algorithm for the P2P proxy cache system although SIZE based cache replacement approach produces slightly better cache hit ratio when cache size is very small. The performance studies also demonstrate that the proposed message routing protocols significantly improve the performance of the P2P cooperative proxy cache system, in terms of cache hit ratio, byte hit ratio, user request latency, and the number of query messages generated in the proxy cache system, compared to the flooding based message routing protocol.

Enabling Service Cache in Edge Clouds

2021 ◽  
Vol 2 (3) ◽  
pp. 1-24
Author(s):  
Chih-Kai Huang ◽  
Shan-Hsiang Shen
Keyword(s):  
Virtual Machines ◽  
Replacement Policy ◽  
Cache Replacement ◽  
Cache Replacement Policy ◽  
Average Latency ◽  
Hit Rates ◽  
Iot Devices ◽  
Multi Access ◽  
Computational Resources ◽  
The Cost

The next-generation 5G cellular networks are designed to support the internet of things (IoT) networks; network components and services are virtualized and run either in virtual machines (VMs) or containers. Moreover, edge clouds (which are closer to end users) are leveraged to reduce end-to-end latency especially for some IoT applications, which require short response time. However, the computational resources are limited in edge clouds. To minimize overall service latency, it is crucial to determine carefully which services should be provided in edge clouds and serve more mobile or IoT devices locally. In this article, we propose a novel service cache framework called S-Cache , which automatically caches popular services in edge clouds. In addition, we design a new cache replacement policy to maximize the cache hit rates. Our evaluations use real log files from Google to form two datasets to evaluate the performance. The proposed cache replacement policy is compared with other policies such as greedy-dual-size-frequency (GDSF) and least-frequently-used (LFU). The experimental results show that the cache hit rates are improved by 39% on average, and the average latency of our cache replacement policy decreases 41% and 38% on average in these two datasets. This indicates that our approach is superior to other existing cache policies and is more suitable in multi-access edge computing environments. In the implementation, S-Cache relies on OpenStack to clone services to edge clouds and direct the network traffic. We also evaluate the cost of cloning the service to an edge cloud. The cloning cost of various real applications is studied by experiments under the presented framework and different environments.

Penalty- and Locality-aware Memory Allocation in Redis Using Enhanced AET

2021 ◽  
Vol 17 (2) ◽  
pp. 1-45
Author(s):  
Cheng Pan ◽  
Xiaolin Wang ◽  
Yingwei Luo ◽  
Zhenlin Wang
Keyword(s):  
Large Data ◽  
Data Locality ◽  
Memory Allocation ◽  
Cache Management ◽  
Cache Replacement ◽  
Time Model ◽  
Memory Cache ◽  
Management Scheme ◽  
Data Volume ◽  
Replacement Algorithms

Due to large data volume and low latency requirements of modern web services, the use of an in-memory key-value (KV) cache often becomes an inevitable choice (e.g., Redis and Memcached). The in-memory cache holds hot data, reduces request latency, and alleviates the load on background databases. Inheriting from the traditional hardware cache design, many existing KV cache systems still use recency-based cache replacement algorithms, e.g., least recently used or its approximations. However, the diversity of miss penalty distinguishes a KV cache from a hardware cache. Inadequate consideration of penalty can substantially compromise space utilization and request service time. KV accesses also demonstrate locality, which needs to be coordinated with miss penalty to guide cache management. In this article, we first discuss how to enhance the existing cache model, the Average Eviction Time model, so that it can adapt to modeling a KV cache. After that, we apply the model to Redis and propose pRedis, Penalty- and Locality-aware Memory Allocation in Redis, which synthesizes data locality and miss penalty, in a quantitative manner, to guide memory allocation and replacement in Redis. At the same time, we also explore the diurnal behavior of a KV store and exploit long-term reuse. We replace the original passive eviction mechanism with an automatic dump/load mechanism, to smooth the transition between access peaks and valleys. Our evaluation shows that pRedis effectively reduces the average and tail access latency with minimal time and space overhead. For both real-world and synthetic workloads, our approach delivers an average of 14.0%∼52.3% latency reduction over a state-of-the-art penalty-aware cache management scheme, Hyperbolic Caching (HC), and shows more quantitative predictability of performance. Moreover, we can obtain even lower average latency (1.1%∼5.5%) when dynamically switching policies between pRedis and HC.

Design of an Intelligent Data Cache with Replacement Policy

2019 ◽  
Vol 10 (2) ◽  
pp. 87-107
Author(s):  
B. Shameedha Begum ◽  
N. Ramasubramanian
Keyword(s):  
Real Time ◽  
Replacement Policy ◽  
Data Cache ◽  
Cache Performance ◽  
Performance Requirements ◽  
Novel Approach ◽  
Reconfigurable Caches ◽  
Real Time Applications ◽  
Hard Real Time ◽  
Replacement Algorithms

Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.

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