scholarly journals DIRECT DIGITAL FREQUENCY SYNTHESIZER IN THE RESIDUE NUMBER SYSTEM

2019 ◽  
pp. 307-315
Author(s):  
Oleksiy Polikarovskykh ◽  
Vasyl Melnychuk ◽  
Ihor Hula ◽  
Lesia Karpova
Keyword(s):  
Frequency Synthesizer ◽  
Number System ◽  
Residue Number System ◽  
Frequency Synthesizers ◽  
Direct Digital Synthesizer ◽  
Number Systems ◽  
Digital Frequency ◽  
Residue Number ◽  
Speed Up ◽  
Direct Digital Frequency Synthesizers

The principles of construction and operation of direct digital frequency synthesizers are considered in order to speed up computational operations using Residue Number System. The problems of forming the output signals are considered. The specifics of the implementation of the operation of direct and reverse transformations from positional to non-positional number systems are described. A mathematical model of a synthesizer with a phase accumulator in a Residue Number System is considered. Methods for converting from RNS (Residue Number System) to binary system for problematic operations are considered. The design of a DDS (Direct Digital Synthesizer) with a phase accumulator in a Residue Number System and a converter to an analogue signal form is proposed without the use of slow ROM (Read Only Memory). The article deals with the issues of efficiency of the crystal area of the synthesizer and the reduction of the delays in the formation of the output signal.

Perspective and Opportunities of Modulo 2n−1 Multipliers in Residue Number System: A Review

2020 ◽  
Vol 29 (11) ◽  
pp. 2030008
Author(s):  
Raj Kumar ◽  
Ritesh Kumar Jaiswal ◽  
Ram Awadh Mishra
Keyword(s):  
Word Length ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
System A ◽  
Essential Components ◽  
Residue Number ◽  
Speed Up ◽  
Computational Circuits

Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo [Formula: see text] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo [Formula: see text] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo [Formula: see text] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.

scholarly journals High-Performance RNS Modular Exponentiation by Sum-Residue Reduction

2020 ◽  
Author(s):  
Tao Wu
Keyword(s):  
High Performance ◽  
Computer Arithmetic ◽  
Number System ◽  
Residue Number System ◽  
Modular Exponentiation ◽  
Number Systems ◽  
Diffie Hellman ◽  
Residue Number ◽  
Diffie Hellman Key Exchange ◽  
Rsa Cryptography

Abstract Modular exponentiation is fundamental in computer arithmetic and is widely applied in cryptography such as ElGamal cryptography, Diffie-Hellman key exchange protocol, and RSA cryptography. Implementation of modular exponentiation in residue number system leads to high parallelism in computation, and has been applied in many hardware architectures. While most RNS based architectures utilizes RNS Montgomery algorithm with two residue number systems, the recent modular multiplication algorithm with sum-residues performs modular reduction in only one residue number system with about the same parallelism. In this work, it is shown that high-performance modular exponentiation and RSA cryptography can be implemented in RNS. Both the algorithm and architecture are improved to achieve high performance with extra area overheads, where a 1024-bit modular exponentiation can be completed in 0.567 ms in Xilinx XC6VLX195t-3 platform, costing 26,489 slices, 87,357 LUTs, 363 dedicated multipilers of $18\times 18$ bits, and 65 Block RAMs.

scholarly journals Data Flow Oriented Hardware Design of RNS-based Polynomial Multiplication for SHE Acceleration

2018 ◽  
pp. 69-88
Author(s):  
Joël Cathébras ◽  
Alexandre Carbon ◽  
Peter Milder ◽  
Renaud Sirdey ◽  
Nicolas Ventroux
Keyword(s):  
Hardware Implementation ◽  
Computation Time ◽  
Number System ◽  
Residue Number System ◽  
Polynomial Multiplication ◽  
Basis Size ◽  
Residue Number ◽  
Speed Up ◽  
Channel Dependent ◽  
Reasonable Use

This paper presents a hardware implementation of a Residue Polynomial Multiplier (RPM), designed to accelerate the full Residue Number System (RNS) variant of the Fan-Vercauteren scheme proposed by Bajard et al. [BEHZ16]. Our design speeds up polynomial multiplication via a Negative Wrapped Convolution (NWC) which locally computes the required RNS channel dependent twiddle factors. Compared to related works, this design is more versatile regarding the addressable parameter sets for the BFV scheme. This is mainly brought by our proposed twiddle factor generator that makes the design BRAM utilization independent of the RNS basis size, with a negligible communication bandwidth usage for non-payload data. Furthermore, the generalization of a DFT hardware generator is explored in order to generate RNS friendly NTT architectures. This approach helps us to validate our RPM design over parameter sets from the work of Halevi et al. [HPS18]. For the depth-20 setting, we achieve an estimated speed up for the residue polynomial multiplications greater than 76 during ciphertexts multiplication, and greater than 16 during relinearization. It thus results in a single-threaded Mult&Relin ciphertext operation in 109.4 ms (×3.19 faster than [HPS18]) with RPM counting for less than 15% of the new computation time. Our RPM design scales up with reasonable use of hardware resources and realistic bandwidth requirements. It can also be exploited for other RNS based implementations of RLWE cryptosystems.

scholarly journals Design of a Modular Multiplier for Public-Key Cryptography Applications Using Residue Number System and Signed-Digit Representation

2020 ◽  
Author(s):  
Mohammad Hizzani
Keyword(s):  
Public Key Cryptography ◽  
Number System ◽  
Residue Number System ◽  
Public Key ◽  
Modular Multiplication ◽  
Secret Key ◽  
Public Key Cryptosystems ◽  
Number Systems ◽  
Wide Range ◽  
Residue Number

Public-Key Cryptosystems are prone to wide range of cryptanalyses due to its property of having key pairs one of them is public. Therefore, the recommended length of these keys is extremely large (e.g. in RSA and D-H the key is at least 2048 bits long) and this leads the computation of such cryptosystems to be slower than the secret-key cryptosystems (i.e. AES and AES-family). Since, the key operation in such systems is the modular multiplication; in this research a novel design for the modular multiplication based on the Montgomery Multiplication, the Residue Number Systems for moduli of any form, and the Signed-Digit Representation is proposed. The proposed design outperforms the current designs in the literature in terms of delay with at least 28% faster for the key of 2048 bits long. Up to our knowledge, this design is the first design that utilizes Signed-Digit Representation with the Residue Number System for moduli of any form.

scholarly journals Improved Perceptual Video Encryption Technique using Residue Number System

2019 ◽  
pp. 111-125
Author(s):  
Salamudeen Alhassan ◽  
Mohammed Muniru Iddrisu ◽  
Mohammed Ibrahim Daabo
Keyword(s):  
Dynamic Range ◽  
Visual Quality ◽  
Number System ◽  
Residue Number System ◽  
Original Video ◽  
Video Encryption ◽  
Reverse Converter ◽  
Residue Number ◽  
Speed Up ◽  
Transmission Speed

In this paper, we propose an enhanced perceptual video encryption technique to speed-up and secure cipher video transmitted across networks using Residue Number System (RNS). The technique proposes a new reverse converter with smaller dynamic range using the moduli set {2n-1, 2n, 2n+1} that is integrated into our previous work of [2]. After encryption, cipher video is encoded into three residual videos that have smaller pixel values and ideal for transmission across networks. Instead of transmitting the three (3) residual videos, the technique effectively transmits and decodes only two (2) of them back into the original video with same visual quality. Experimental results show that the technique enhances transmission speed and security of cipher video across networks.

scholarly journals Montgomery reduction within the context of residue number system arithmetic

2017 ◽  
Vol 8 (3) ◽  
pp. 189-200 ◽  
Author(s):  
Jean-Claude Bajard ◽  
Julien Eynard ◽  
Nabil Merkiche
Keyword(s):  
Number System ◽  
Residue Number System ◽  
Residue Number ◽  
Montgomery Reduction

scholarly journals Computationally Efficient Approach to Implementation of the Chinese Remainder Theorem Algorithm in Minimally Redundant Residue Number System

2021 ◽  
Author(s):  
Mikhail Selianinau
Keyword(s):  
Chinese Remainder Theorem ◽  
Number System ◽  
Residue Number System ◽  
Computer Applications ◽  
Efficient Approach ◽  
Residue Modulo ◽  
Modern Computer ◽  
New Variant ◽  
Residue Number ◽  
Residue Code

AbstractIn this paper, we deal with the critical problem of performing non-modular operations in the Residue Number System (RNS). The Chinese Remainder Theorem (CRT) is widely used in many modern computer applications. Throughout the article, an efficient approach for implementing the CRT algorithm is described. The structure of the rank of an RNS number, a principal positional characteristic of the residue code, is investigated. It is shown that the rank of a number can be represented by a sum of an inexact rank and a two-valued correction to it. We propose a new variant of minimally redundant RNS, which provides low computational complexity for the rank calculation, and its effectiveness analyzed concerning conventional non-redundant RNS. Owing to the extension of the residue code, by adding the excess residue modulo 2, the complexity of the rank calculation goes down from $O\left (k^{2}\right )$ O k 2 to $O\left (k\right )$ O k with respect to required modular addition operations and lookup tables, where k equals the number of non-redundant RNS moduli.

The residue number system

1959 ◽  
Author(s):  
Harvey L. Garner
Keyword(s):  
Number System ◽  
Residue Number System ◽  
Residue Number
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