Evolutionary Synthesis of Failure-Resilient Analog Circuits

Analog circuit design requires large amounts of human knowledge. A special case of circuit design is the synthesis of robust and failure-resilient electronics. Evolutionary algorithms can aid designers in exploring topologies with new properties. Here, we show how to encode a circuit topology with an upper-triangular incident matrix and use the NSGA-II algorithm to find computational circuits that are robust to component failure. Techniques for robustness evaluation and evolutionary algorithm guidances are described. As a result, we evolve square root and natural logarithm computational circuits that are robust to high-impedance or short-circuit malfunction of an arbitrary rectifying diode. We confirm the simulation results by hardware circuit implementation and measurements. We think that our research will inspire further searches for failure-resilient topologies.

On a new four-dimensional model of memristor-based chaotic circuit in the context of nonsingular Atangana–Baleanu–Caputo operators

A memristor is naturally a nonlinear and at the same time memory element that may substitute resistors for next-generation nonlinear computational circuits that can show complex behaviors including chaos. A four-dimensional memristor system with the Atangana–Baleanu fractional nonsingular operator in the sense of Caputo is investigated. The Banach fixed point theorem for contraction principle is used to verify the existence–uniqueness of the fractional representation of the given system. A newly developed numerical scheme for fractional-order systems introduced by Toufik and Atangana is utilized to obtain the phase portraits of the suggested system for different fractional derivative orders and different parameter values of the system. Analysis on the local stability of the fractional model via the Matignon criteria showed that the trivial equilibrium point is unstable. The dynamics of the system are investigated using Lyapunov exponents for the characterization of the nature of the chaos and to verify the dissipativity of the system. It is shown that the supposed system is chaotic and it is significantly sensitive to parameter variation and small initial condition changes.

Efficient circuit design for content-addressable memory in quantum-dot cellular automata technology

Quantum-dot cellular automata (QCA) technology is a kind of nanotechnology utilized for building computational circuits. It can be a good technology for overcome CMOS drawbacks at nano-scale due to its low delay and area. The Content-Addressable Memory (CAM) is a very fast memory that can perform search operations in a very short time. This feature makes the relative popularity of these memories and many applications for them, especially in network routing and processors. In this study, a novel loop-based circuit is designed for the QCA memory unit, which reduces area, cell count, latency, and cost. The obtained results using QCADesigner tool version 2.0.3 demonstrate that the designed QCA memory unit utilizes 16 cells, 0.01 µm2 area, and 0.25 clock cycles and has a reduction of 33% in the number of cells, 50% in area, 50% in latency, and 75% in cost compared to existing works. Then, this memory unit is utilized to design an efficient structure for CAM circuit. The results show that the developed structure for CAM circuit has 0.75 clock cycles, 32 cells, and 0.03 µm2 area, and it has a reduction of 20% in the number of cells, 25% in area, 40% in latency, and 75% in cost compared to existing works.

Photochemical NOT Gate for DNA Computing

DNA-based Boolean logic gates (AND, OR and NOT) can be assembled into complex computational circuits that generate an output signal in response to specific patterns of oligonucleotide inputs. However, the fundamental nature of NOT gates, which convert the absence of an input into an output, makes their implementation within DNA-based circuits difficult. Premature execution of a NOT gate before completion of its upstream computation introduces an irreversible error into the circuit. We developed a novel DNA gate design utilizing photocaging groups that prevents gate function until irradiation at a certain time-point. Optical activation provides temporal control over circuit performance by preventing premature computation and is orthogonal to all components of DNA computation devices. Using this approach, we designed NAND and NOR logic gates that respond to synthetic microRNA inputs. We further demonstrate the utility of the NOT gate within multi-layer circuits in response to a specific pattern of four microRNAs.

Approximate 5-2 Compressor Cell Using Spin-Based Majority Gates

One of the most interesting solutions for decreasing the static power of computational circuits is to use approximate computing. Approximate computing has been extensively considered to trade-off limited accuracy for improvements in other circuit metrics such as area, power and performance. On the other hand, the increasing leakage power and limited scalability have become serious obstacles that prevent the continuous miniaturization of conventional CMOS-based logic circuits. Spintronic devices are being considered as a promising alternative technology for silicon-based FET to implement digital circuits. In this paper, an approximate 5-2 compressor cell is presented using spin-based devices. The proposed circuit is designed by majority gates which can be implemented very easily and efficiently by spintronic threshold device (STD). The proposed design has been simulated comprehensively for both quantitative and qualitative metrics. The results show that the spin-based compressor decreases the power consumption about 7X compared to the best state-of-the-art design. Also, the application simulations using the multiplier implemented by the proposed compressor indicate the acceptable results.

Perspective and Opportunities of Modulo 2n−1 Multipliers in Residue Number System: A Review

Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo [Formula: see text] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo [Formula: see text] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo [Formula: see text] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.