Impedance Cytometry for Detection of Particle and Counting using Low Phase Noise DDFS – LUT

The biotechnology is widely growing with many technologies, still we see a large gap in real-time implementation of complete blood counting. To increase the resolution and accuracy of the measurements advanced communication DDFS can be used. The elements in Direct Digital Frequency Synthesizers (DDFS) involved are: phase accumulator, a phase to amplitude converter which also called look up table (LUT), a digital to analog converter along with active filter. Direct digital frequency synthesis is a method for generating complex high - frequency waveforms for specific applications. This DDFS generates frequency resolution which makes it ideal components use in radar system, software defined radio, modern wireless communicating system, advanced satellite navigation purpose. Use cases for high frequency we get interrupt with spurious noise, larger ROM size, and high power consumption of DDFS signal. In this paper we are proposing the use of signal generated from DDFS to impedance cytometry in which the number of particles gets detected by getting the output frequency different from the input frequency. Due to use of small frequency range of signal spurious noise, power consumption and ROM size will be less with effective performance

DIRECT DIGITAL FREQUENCY SYNTHESIZER IN THE RESIDUE NUMBER SYSTEM

The principles of construction and operation of direct digital frequency synthesizers are considered in order to speed up computational operations using Residue Number System. The problems of forming the output signals are considered. The specifics of the implementation of the operation of direct and reverse transformations from positional to non-positional number systems are described. A mathematical model of a synthesizer with a phase accumulator in a Residue Number System is considered. Methods for converting from RNS (Residue Number System) to binary system for problematic operations are considered. The design of a DDS (Direct Digital Synthesizer) with a phase accumulator in a Residue Number System and a converter to an analogue signal form is proposed without the use of slow ROM (Read Only Memory). The article deals with the issues of efficiency of the crystal area of the synthesizer and the reduction of the delays in the formation of the output signal.

BBR-Based Iteration-Free CORDIC Algorithm

Coordinate rotation digital computer (CORDIC) algorithm has been widely used in modern digital communication systems such as all-digital phase-locked loop, fast Fourier transform and direct digital frequency synthesizers. Precision of the CORDIC algorithm implemented using pipelined architecture has to be guaranteed by increasing the number of iterations, which leads to large delay, excessive consumption of hardware resource and other problems, unfavorable for applications calling for high real-time performance and low power consumption. In this paper, through integrated use of binary to bipolar recoding, angle domain folding, merging iteration and optimized lookup table, an iteration-free CORDIC algorithm was proposed, with which it takes only two clock cycles to get the output, and it enables certain improvements in hardware consumption and output precision when compared with other basic implementation methods.