scholarly journals Magnetic-field CMOS microsensor for low-energy electric discharge detection

2018 ◽  
Vol 7 (2) ◽  
pp. 569-575
Author(s):  
Mohamed Hadj Said ◽  
Farès Tounsi ◽  
Libor Rufer ◽  
Hatem Trabelsi ◽  
Brahim Mezghani ◽  
...  

Abstract. This paper addresses the development and characterization of a non-intrusive silicon-based microsensor, which can detect electric partial discharges in electrical insulation equipment. Early partial discharge detection prevents failures and can be used to optimize maintenance operations. Despite the potential that CMOS technology offers, miniaturized electric discharge detector has neither been investigated nor implemented, until now. The developed microsensor demonstrates its ability to record electric discharge emission thanks to the presence of a miniaturized planar inductor. The squared inductor of 50 turns with a side length of 1.5 mm used in our sensor has been fabricated on top of a silicon substrate in a CMOS technology. The total inductor wire length of loop antenna is 30 cm to achieve 100 MHz bandwidth. Using the microsensor at 1 cm from the discharge site, a damped sinusoidal induced voltage with an amplitude of 2 V has been measured at its output. We observed that the output signal spectrum is highly concentrated around a central resonance frequency, which remains constant. The main advantage of such design resides in its monolithic integration added to the high autonomy, which improves the microsensor efficiency.

Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.


2020 ◽  
Vol 11 (3) ◽  
pp. 364-364
Author(s):  
Maciej Ratynski ◽  
Bartosz Hamankiewicz ◽  
Michał Krajewski ◽  
Maciej Boczar ◽  
Dominika A. Buchberger ◽  
...  

2012 ◽  
Vol 108 ◽  
pp. 50-59 ◽  
Author(s):  
Christos Tsabaris ◽  
Dionisis L. Patiris ◽  
Aristomenis P. Karageorgis ◽  
George Eleftheriou ◽  
Vassilis P. Papadopoulos ◽  
...  

Author(s):  
Jixin Chen ◽  
Weitian Liu ◽  
Pinpin Yan ◽  
Chenwei Jia ◽  
Debing Hou ◽  
...  

Nanophotonics ◽  
2014 ◽  
Vol 3 (4-5) ◽  
pp. 329-341 ◽  
Author(s):  
Raji Shankar ◽  
Marko Lončar

AbstractThe mid-infrared (IR) wavelength region (2–20 µm) is of great interest for a number of applications, including trace gas sensing, thermal imaging, and free-space communications. Recently, there has been significant progress in developing a mid-IR photonics platform in Si, which is highly transparent in the mid-IR, due to the ease of fabrication and CMOS compatibility provided by the Si platform. Here, we discuss our group’s recent contributions to the field of silicon-based mid-IR photonics, including photonic crystal cavities in a Si membrane platform and grating-coupled high-quality factor ring resonators in a silicon-on-sapphire (SOS) platform. Since experimental characterization of microphotonic devices is especially challenging at the mid-IR, we also review our mid-IR characterization techniques in some detail. Additionally, pre- and post-processing techniques for improving device performance, such as resist reflow, Piranha clean/HF dip cycling, and annealing are discussed.


2014 ◽  
Vol 1691 ◽  
Author(s):  
Alexandre Savtchouk ◽  
John D’Amico ◽  
Marshall Wilson ◽  
Jacek Lagowski ◽  
Wei-E Wang ◽  
...  

ABSTRACTWe report the first successful application of corona charging noncontact C-V and I-V metrology to interface and dielectric characterization of high-k/III-V structures. The metrology, which has been commonly used in Si IC manufacturing, uses incremental corona charge dosing, ΔQC, on the dielectric surface, and the measurement of surface voltage response, ΔVS, using a Kelvin-probe. Its application to In0.53Ga0.47As with a high-k stack required modifications related to the effects of dielectric trap induced voltage transients. The developed Corona Charge-Kelvin Probe Metrology adopted strictly differential measurements using ΔQC and ΔV, and corresponding differential capacitance rather than measurements based on total global charge, Q, and voltage, V, values.Electrical characterization data including interface trap density, electrical oxide thickness, and dielectric leakage are presented for a sample containing an In0.53 Ga0.47 As channel overlaid with a bilayer (2nm Al2O3/5nm HfO2) dielectric stack that is considered to be very promising for application in performance NFETs with high-mobility channels.


Author(s):  
Q. Courte ◽  
M. Rack ◽  
M. Nabet ◽  
P. Cardinael ◽  
J.-P. Raskin
Keyword(s):  

Author(s):  
Yolanda Fintschenko ◽  
Patrick Fowler ◽  
Vincent Spiering ◽  
Gert-Jan Burger ◽  
Albert van den Berg

2022 ◽  
pp. 11-43
Author(s):  
Gautam M. Patel ◽  
Gaurang J. Bhatt ◽  
Pradeep T. Deota

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