Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

2014 ◽  
Author(s):  
Yuk L. Tsang ◽  
Alex VanVianen ◽  
Xiang D. Wang ◽  
N. David Theodore
Keyword(s):  
Threshold Voltage ◽  
Crystalline Silicon ◽  
Electrical Characterization ◽  
Visual Defect ◽  
Scanning Capacitance Microscopy ◽  
Device Model ◽  
Graphical Simulation ◽  
Cmos Transistor

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.

Interface Interstitial Recombination Rate and the Reverse Short Channel Effect

1999 ◽  
Vol 568 ◽  
Author(s):  
M.E. Rubin ◽  
S. Saha ◽  
J. Lutze ◽  
F. Nouri ◽  
G. Scott ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Recombination Rate ◽  
Gate Oxide ◽  
Two Dimensional ◽  
Short Channel ◽  
Short Channel Effect ◽  
Mos Capacitor ◽  
Enhanced Diffusion ◽  
Channel Effect ◽  
Additional Nitrogen

ABSTRACTExperiment shows that the reverse short channel effect (RSCE) in nMOS devices is critically impacted by the inclusion of nitrogen in the gate oxide. A higher concentration of nitrogen results in a lessened RSCE, i.e. more threshold voltage rolloff for smaller gate lengths. We propose that the additional nitrogen reduces the interstitial recombination rate at the interface, resulting in a smaller interstitial flux and therefore less transient enhanced diffusion (TED) of boron to that interface. To test this hypothesis, we simulate boron redistribution in one and two dimensional MOS capacitor structures, as well as full nMOS devices. We then present simulations calibrated to a 0.2 pim technology currently in production.

Effects of Compositional Segregation and Short Channel on Threshold Voltage of nMOSFET

1997 ◽  
Vol 490 ◽  
Author(s):  
Julie Y. H. Lee ◽  
Tom C. H. Lee ◽  
Mike Embry ◽  
Keenan Evans ◽  
Dan Koch ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Doping Concentration ◽  
Channel Length ◽  
Drift Diffusion ◽  
Short Channel ◽  
Short Channel Effect ◽  
Dopant Segregation ◽  
Channel Effect ◽  
Substrate Doping ◽  
Compositional Segregation

ABSTRACTThis study calculates the threshold voltage (VT) roll-off behavior caused by short channel effect (SCE) as a result of scaling and the reverse short-channel effect (RSCE) due to B segregation around source and drain junctions by using the 2D device simulator - SILVACO™-ATLAS. The simulation results are comparable with the experimental data. It suggests that the drift diffusion physics can predict SCE and RSCE very well to sub-0.25μ Si n-MOSFET devices. The modeling results indicate the VT roll off at shorter channel length for devices with higher substrate doping concentration. VT increases if the local p-dopant segregation exists around the source and drain junction. It is observed that RSCE is more significant for devices with lower substrate doping concentration and shorter channel length.

Reverse short-channel effect of threshold voltage in LOCOS parasitic MOSFETs

1995 ◽  
Vol 38 (3) ◽  
pp. 567-572 ◽  
Author(s):  
Junko Tanaka ◽  
Toru Toyabe ◽  
Hitoshi Matsuo ◽  
Sigeo Ihara ◽  
Hiroo Masuda ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect

Suppression of Short-Channel Effects in 4H-SiC Trench MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 613-616
Author(s):  
Tomoyasu Ishii ◽  
Shinichiro Kuroki ◽  
Hiroshi Sezaki ◽  
Seiji Ishikawa ◽  
Tomonori Maeda ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Threshold Voltage ◽  
High Frequency ◽  
Short Channel Effects ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Channel Effects ◽  
Trench Structure ◽  
High Frequency Operation

Submicron 4H-SiC MOSFETs are attractive for high frequency operation of 4H-SiC integrated circuits. However, the short channel effects, such as threshold voltage lowering, would be induced at the short-channel devices. In this work, short channel effects were investigated with planar and trench 4H-SiC MOSFETs, and the suppression of the short channel effect with the trench structure was achieved.

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