2007 IEEE International Electron Devices Meeting
Latest Publications

TOTAL DOCUMENTS

281

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781424415076

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4418914 ◽

2007 ◽

Cited By ~ 296

Author(s):

K. Mistry ◽

R. Chau ◽

C.-H. Choi ◽

G. Ding ◽

K. Fischer ◽

...

Keyword(s):

Strained Silicon ◽

Metal Gate ◽

High K ◽

Cu Interconnect

Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4418868 ◽

2007 ◽

Cited By ~ 7

Author(s):

J. Fu ◽

K. D. Buddharaju ◽

S. H. G. Teo ◽

Chunxiang Zhu ◽

M. B. Yu ◽

...

Keyword(s):

Nonvolatile Memory ◽

Si Nanowire

Electrical measurement of adhesion and viability of living cells with a silicon chip

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4419083 ◽

2007 ◽

Author(s):

L. Bandiera ◽

M. Borgo ◽

G. Cellere ◽

A. De Toni ◽

L. Santoni ◽

...

Keyword(s):

Electrical Measurement ◽

Living Cells

Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4419048 ◽

2007 ◽

Cited By ~ 30

Author(s):

Duygu Kuzum ◽

Abhijit J. Pethe ◽

Tejas Krishnamohan ◽

Yasuhiro Oshima ◽

Yun Sun ◽

...

Keyword(s):

High Mobility

SiGe BiCMOS Technology with 3.0 ps Gate Delay

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4419028 ◽

2007 ◽

Cited By ~ 14

Author(s):

H. Rucker ◽

O. Fursenko ◽

T. Grabolla ◽

U. Haak ◽

W. Hoppner ◽

...

Keyword(s):

Gate Delay ◽

Bicmos Technology ◽

Sige Bicmos

More-than-Universal Mobility in Double-Gate SOI p-FETs with Sub-10-nm Body Thickness -Role of Light-Hole Band and Compatibility with Uniaxial Stress Engineering

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4419044 ◽

2007 ◽

Cited By ~ 2

Author(s):

Shigeki Kobayashi ◽

Masumi Saitoh ◽

Ken Uchida

Keyword(s):

Uniaxial Stress ◽

Light Hole ◽

Double Gate ◽

Stress Engineering ◽

Hole Band ◽

Role Of Light

Physical Understanding of Fundamental Properties of Si (110) pMOSFETs Inversion-Layer Capacitance, Mobility Universality, and Uniaxial Stress Effects

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4419045 ◽

2007 ◽

Cited By ~ 13

Author(s):

Masumi Saitoh ◽

Shigeki Kobayashi ◽

Ken Uchida

Keyword(s):

Inversion Layer ◽

Uniaxial Stress ◽

Stress Effects ◽

Fundamental Properties ◽

Physical Understanding

Integration Technology of PC-FUSI (Phase Controlled FUSI) / HfSiON Gate Stack for Embedded Memory Application

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4418865 ◽

2007 ◽

Author(s):

Motofumi Saitoh ◽

Takashi Ogura ◽

Koji Masuzaki ◽

Kensuke Takahashi ◽

Hiroshi Sunamura ◽

...

Keyword(s):

Embedded Memory ◽

Gate Stack ◽

Integration Technology

FBC's Potential of 6F2 Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4418857 ◽

2007 ◽

Cited By ~ 5

Author(s):

Fumiyoshi Matsuoka ◽

Takashi Ohsawa ◽

Tomoki Higashi ◽

Hironobu Furuhashi ◽

Kosuke Hatsuda ◽

...

Keyword(s):

Single Cell ◽

Measuring Signal

Ultra-Low Leakage Silicon-on-Insulator Technology for 65 nm Node and Beyond

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4419097 ◽

2007 ◽

Cited By ~ 2

Author(s):

Jin Cai ◽

Amlan Majumdar ◽

David Dobuzinsky ◽

Tak H. Ning ◽

Steven J. Koester ◽

...

Keyword(s):

Silicon On Insulator ◽

Low Leakage ◽

Silicon On Insulator Technology

2007 IEEE International Electron Devices MeetingLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory

Electrical measurement of adhesion and viability of living cells with a silicon chip

Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility

SiGe BiCMOS Technology with 3.0 ps Gate Delay

More-than-Universal Mobility in Double-Gate SOI p-FETs with Sub-10-nm Body Thickness -Role of Light-Hole Band and Compatibility with Uniaxial Stress Engineering

Physical Understanding of Fundamental Properties of Si (110) pMOSFETs Inversion-Layer Capacitance, Mobility Universality, and Uniaxial Stress Effects

Integration Technology of PC-FUSI (Phase Controlled FUSI) / HfSiON Gate Stack for Embedded Memory Application

FBC's Potential of 6F2 Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin

Ultra-Low Leakage Silicon-on-Insulator Technology for 65 nm Node and Beyond

2007 IEEE International Electron Devices Meeting
Latest Publications