Effect of Dynamic Bias Stress in Short-Channel (L=1.5 µm) p-Type Polycrystalline Silicon Thin-Film Transistors

2012 ◽  
Vol 51 (2R) ◽  
pp. 021401
Author(s):  
Sung-Hwan Choi ◽  
Yeon-Gon Mo ◽  
Hye-Dong Kim ◽  
Min-Koo Han
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Silicon Thin Film ◽  
Short Channel ◽  
Bias Stress ◽  
P Type ◽  
Dynamic Bias

Effect of Dynamic Bias Stress (AC) In Short-Channel (L=1.5μm) p-Type polycrystalline Silicon (poly-Si) Thin Film Transistors (TFTs) on the glass substrate

2011 ◽  
Vol 1321 ◽  
Author(s):  
Sung-Hwan Choi ◽  
Yeon-Gon Mo ◽  
Min-Koo Han
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Glass Substrate ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Short Channel ◽  
Bias Stress ◽  
P Type ◽  
Long Channel ◽  
Si Thin Film

ABSTRACTWe have investigated the stability of short channel (1.5μm) p-Type polycrystalline silicon (poly-Si) Thin Film Transistors (TFTs) on the glass substrate under AC bias stress. The variation of threshold voltage in short channel poly-Si TFT was considerably higher than that of long channel poly-Si TFT. Threshold voltage of the short channel TFT was considerably moved to the positive direction during AC bias stress, whereas the threshold voltage of a long channel was rarely moved. The variation of threshold voltage in the short channel p-type TFT under AC bias stess was more compared to that under DC bias stress. The threshold voltage of short channel (L=1.5μm) poly-Si TFT was increased about -7.44V from -0.305V to -7.745V when VGS = 5 (base value) ~ -15V (peak value), VDS = -15V was applied for 3,000 seconds. This positive shift of threshold voltage and significantly degraded s-swing value in the short channel TFT under dynamic stress (AC) may be due to the increase of the stress-induced trap state density at gate insulator / channel interface region.

Reliability in Short-Channel p-Type Polycrystalline Silicon Thin-Film Transistor under High Gate and Drain Bias Stress

2010 ◽  
Vol 49 (3) ◽  
pp. 03CA04 ◽  
Author(s):  
Sung-Hwan Choi ◽  
Sun-Jae Kim ◽  
Yeon-Gon Mo ◽  
Hye-Dong Kim ◽  
Min-Koo Han
Keyword(s):  
Thin Film ◽  
Polycrystalline Silicon ◽  
Thin Film Transistor ◽  
Silicon Thin Film ◽  
Short Channel ◽  
Bias Stress ◽  
Drain Bias ◽  
P Type

Analysis of low frequency noise characteristics in p-type polycrystalline silicon thin film transistors

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740020
Author(s):  
Yuan Liu ◽  
Yun-Fei En ◽  
Wen-Xiao Fang
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Low Frequency ◽  
Gate Oxide ◽  
Localized States ◽  
Frequency Noise ◽  
Silicon Thin Film ◽  
Noise Characteristics ◽  
P Type

Low frequency noises in the p-type polycrystalline silicon thin film transistors are investigated. It shows a pure 1/f[Formula: see text] (with [Formula: see text] near one) noise behavior which can be explained by emission and trapping processes of carriers between trapping states. Subsequently, the gate voltage-dependent drain current noise power spectral densities closely follow the mobility fluctuation model, and the average Hooge’s parameter is then extracted. By considering traditional tunneling processes, the flat-band voltage spectral density is extracted and the concentration of traps in the grain boundary is calculated to be [Formula: see text]. By converting the frequency to tunneling depth of carriers in the gate oxide, the spatial distribution of gate oxide trapped charges are obtained. Finally, the distribution of localized states in the energy band is extracted. The experimental results show an exponential deep states and tail states distribution in the band gap while [Formula: see text] is about [Formula: see text], [Formula: see text] is [Formula: see text][Formula: see text]617 K, [Formula: see text] is [Formula: see text] and [Formula: see text] is [Formula: see text][Formula: see text]265 K.

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