Paving the Way for Tunable Graphene Plasmonic THz Amplifiers

This study reviews recent advances in room-temperature coherent amplification of terahertz (THz) radiation in graphene, electrically driven by a dry cell battery. Our study explores THz light–plasmon coupling, light absorption, and amplification using a current-driven graphene-based system because of its excellent room temperature electrical and optical properties. An efficient method to exploit graphene Dirac plasmons (GDPs) for light generation and amplification is introduced. This approach is based on current-driven excitation of the GDPs in a dual-grating-gate high-mobility graphene channel field-effect transistor (DGG-GFET) structure. The temporal response of the DGG-GFETs to the polarization-managed incident THz pulsation is experimentally observed by using THz time-domain spectroscopy. Their Fourier spectra of the transmitted temporal waveform through the GDPs reveals the device functions 1) resonant absorption at low drain bias voltages below the first threshold level, 2) perfect transparency between the first and the second threshold drain bias levels, and 3) resonant amplification beyond the second threshold drain bias voltage. The maximal gain of 9% is obtained by a monolayer graphene at room temperatures, which is four times higher than the quantum limit that is given when THz photons directly interact with electrons. The results pave the way toward tunable graphene plasmonic THz amplifiers.

Skin-Compatible Amorphous Oxide Thin-Film-Transistors with a Stress-Released Elastic Architecture

A highly reliable reverse-trapezoid-structured polydimethylsiloxane (PDMS) is demonstrated to achieve mechanically enhanced amorphous indium-gallium-zinc oxide (a-IGZO) thin-film-transistors (TFTs) for skin-compatible electronics. Finite element analysis (FEA) simulation reveals that the stress within a-IGZO TFTs can be efficiently reduced compared to conventional substrates. Based on the results, a conventional photolithography process was employed to implement the reverse-trapezoid homogeneous structures using a negative photoresist (NPR). Simply accessible photolithography using NPR enabled high-resolution patterning and thus large-area scalable device architectures could be obtained. The a-IGZO TFTs on the reverse-trapezoid-structured PDMS exhibited a maximum saturation mobility of 6.06 cm2V−1s−1 under a drain bias voltage of 10 V with minimal strain stress. As a result, the proposed a-IGZO TFTs, including stress-released architecture, exhibited highly enhanced mechanical properties, showing saturation mobility variation within 12% under a strain of 15%, whereas conventional planar a-IGZO TFTs on PDMS showed mobility variation over 10% even under a 1% strain and failed to operate beyond a 2% strain.

The Extraction of Polyoxometalate Flash Compact Model and Corresponding Circuit Simulation

The main component of the POM flash memories is a polyoxometalates (POMs) layer which is used as the floating gate. As a competitive candidate of NAND Flash, POM flash memories attract significant interest and intensive investigations which have been conducted on modelling its physical characteristics and electrical properties. In this paper, we report the development of a specific compact model extraction strategy for POM flash memory based on BSIM4 compact model, allowing the corresponding circuit performance investigation. POM flash compact models are extracted and optimized using genetic algorithm (GA) at the three POM flash redox states. The extracted models are in good agreement with both high drain and low drain bias TCAD simulations. For the first time, the extracted compact models are applied in the circuit simulation to investigate the circuit behaviour of POM flash cells. This will provide valuable guidance for the practical design using POM flash cells.

Noise Immune Dielectric Modulated Dual Trench Transparent Gate Engineered MOSFET as a Label Free Biosensor: Proposal and Investigation

In this work, we have examined and proposed a dielectrically modulated biosensor based on the dual trench transparent gate engineered MOSFET (DM DT GE-MOSFET) for label-free detection of biomolecules with enhanced sensitivity and efficiency. Different sensing parameters such as the ION/IOFF, threshold voltage shift have been evaluated to validate the sensing metric for the proposed device. Additionally, the SVth (Vth Sensitivity) has been also analyzed by considering the charged (positive and negative) biomolecules. In addition to this, the RF sensing parameters such as the transconductance gain and cut-off frequency have been also taken into account to provide a better insight into the sensitivity analysis of the proposed device. Furthermore, the linearity, distortion and noise immunity of the device has been evaluated to check the overall performance of the biosensor at high frequency (GHz). Moreover, the results indicate that, the proposed biosensor exhibits a SVth of 0.68 for the positively charged biomolecules at a very low drain bias (0.2 V). Therefore, the proposed device can be used as an alternative to the conventional FET-based biosensors.

New single-electron pump regime with highly controllable plateaus

Future quantum based electronic systems will demand robust and highly accurate on-demand sources of current. Generating quantised current has immediate implications for quantum computing, quantum metrology, and electron interferometry. The ultimate limit of quantised current sources is a highly controllable device that manipulates individual electrons. We present a new single-electron pump mechanism, realised in a GaAs two-dimensional electron gas, where electrons are pumped through a one-dimensional split-gate confinement potential rather than more conventionally over a finger-gate potential. This new mechanism yields a new long pumping regime with quantised plateaus that are over two orders of magnitude longer than conventional pumps, and are extremely stable with respect to the applied voltages on the gates. The long plateaus are achieved via the combination of a saddle-point potential profile and enhanced quantum tunnelling, wherein the potential barrier height and shape are modified by the application of a source-drain bias. This new pumping regime cannot be explained by the simple geometrical electrostatic models or back-tunnelling theory that are used to describe conventional single-electron pumps, and we use a simple electrostatic model applied to split-gate confined pumps to explain some of the source-drain bias dependence.

Direct white noise characterization of short-channel MOSFETs

On-wafer evaluation of white thermal and shot noise in nanoscale MOSFETs is demonstrated by directly sensing the drain current under zero- and nonzsero-drain-bias (V_d) conditions for the first time, without recourse to a hot noise source, commonly needed in noise figure measurement. The dependence of white noise intensity on the drain bias clearly shows thermal noise at V_d=0 V and shot noise at V_d>0 V with its gate-bias-dependent suppression. An empirical expression for the Fano factor (shot-noise suppression factor) that is well-behaved even at V_d=0V exactly and suitable for measurement-based evaluation is proposed. The direct measurement approach could allow more accurate and predictive noise modeling of RF MOSFETs than has conventionally been possible.

A Quasi 2-D Electrostatic Potential and Threshold Voltage Model for Junctionless Triple Material Cylindrical Surrounding Gate Si Nanowire Transistor

A mathematical model used for determining the threshold voltage characteristics and electrostatic potential of a Junctionless Triple Material Cylindrical Surrounding Gate Silicon Nanowire Transistor (JLTMCSGSiNWT) is proposed in this research work and is obtained by resolving the poison equation. Three materials with dissimilar metal functions are used in the construction of the device gate structure. Device parameters used to determine the electrical characteristics are also included in the model. Behavior of the device is investigated through its vertical electrical field distribution along the device channel. Higher drain bias conditions leading to DIBL are reduced in the proposed structure by minimal variation of voltages owing to three different gate materials that maintain a steady field distribution along the channel. This model explicitly shows the impact of various criteria like drain bias voltage, gate bias voltage, thickness of the silicon layer, thickness of the oxide layer, and length of the channel on electrostatic potential and the deterioration of threshold voltage. The proposed analytical model is validated with TCAD simulations and it could be further extended to study the advanced electrical characteristics of the JL Triple Material CSG Silicon Nanowire Transistor.