Emulation of high-frequency substrate noise generation in CMOS digital circuits

2014 ◽  
Vol 53 (4S) ◽  
pp. 04EE06
Author(s):  
Shunsuke Shimazaki ◽  
Shota Taga ◽  
Tetsuya Makita ◽  
Naoya Azuma ◽  
Noriyuki Miura ◽  
...  
Keyword(s):  
High Frequency ◽  
Digital Circuits ◽  
Noise Generation ◽  
Substrate Noise

Emulation of High Frequency Substrate Noise in CMOS Digital Circuits with Effects of Adjusting Clock Skew

2013 ◽  
Author(s):  
S. Shimazaki ◽  
S. Taga ◽  
T. Makita ◽  
N. Azuma ◽  
N. Miura ◽  
...  
Keyword(s):  
High Frequency ◽  
Digital Circuits ◽  
Substrate Noise ◽  
Clock Skew

SWAN: high-level simulation methodology for digital substrate noise generation

2006 ◽  
Vol 14 (1) ◽  
pp. 23-33 ◽  
Author(s):  
M. Badaroglu ◽  
G. Van der Plas ◽  
P. Wambacq ◽  
S. Donnay ◽  
G.G.E. Gielen ◽  
...  
Keyword(s):  
Noise Generation ◽  
Substrate Noise ◽  
Simulation Methodology ◽  
High Level
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