Analog based Neuromorphic Systems on Low Power Current Mode Circuits

Neuromorphic computing is the process used to appliance the neural system models. Formerly, it is referred to as the biological process and later it turned out to be the computing algorithms. Many neuromorphic algorithms represented as the neural figures such as neural spikes, fluctuated graphs, and synapses. The biological nervous system for instance consists of huge number of neurons and they collectively work to encode the stimulus of various senses. In case of neuromorphic computing, automated brain brings in the concept of efficient work carried out through artificial means. The neuromorphic computing thus evolves as a major technological advancement and the need of such technique is the need of the hour in various scientific as well as field applications. In existing techniques, the scaling, power and area are not efficient. This study attempts to address the major issues such as scaling and power. This paper explains the design on a non-spiking network which is used for population coding architecture. The model which is discussed in this paper is based on the analog domain and the current mode circuits are also involved. The input neuron model consists of current direction selector block, current scale block and minimum current block which all comprise to form the neuron model. This paper also brings out the possible outcome of low power constraints. This paper involves 180nm technology with which the power is measured. This paper brings out the simulations of both 180 and 90nm technologies. Apart from current scale block, minimum current block and current direction selector block, there are other blocks such as current splitter block and current mode low pass filter block, where all the circuits work under the sub-threshold condition. The power consumption obtained in the 180 nm technology is 58.838 µW and its energy equivalent is 1.765pJ. Neuromorphic computing is used as an application where the machines are being automated and such machines come with self-thinking capability. Neuromorphic computing design which is evolved from this paper is found to be more power ad energy efficient. The tool used is Cadence Virtuoso.

Time Dimensional Consistency Aware Analysis of Voltage Mode and Current Mode Active Fractional Circuits

In this research, the analysis of the active fractional circuits has been performed by using the fractional differential equation approach. Both voltage and current mode circuits have been taken into account. The fractional time component parameters have been included in the derivative terms within the fractional differential equations. This is because the consistency in time dimension between the fractional derivative and the conventional one which is also related to the physical measurability, is concerned. The fractional derivatives have been interpreted in Caputo sense. The resulting analytical solutions of the time dimensional consistency aware fractional differential equations have been determined. We have found that the dimensional consistency between both sides of the equations of the solutions which cannot be achieved in the previous works, can be obtained. By applying different source terms to the obtained analytical solutions, the response of both voltage and current mode circuits have been determined and the behaviours of the circuits have been analysed. The fractional time constant and pole locations in the F-plane of these circuits have been determined. Their dynamic behaviours, stabilities have been analysed. Moreover, the discussion on circuit realizations with fractional capacitor has also been made.

Modeling and Sizing of Power-Gating Single-Rail MOS Current Mode Logic

Almost all power-gating circuits used in MOS current-mode circuits were realized with dual-rail schemes. In this paper, a power-gating scheme for single-rail MOS current mode logic (SRMCML) is presented. The modeling of the sleep transistor in power-gating circuits is constructed and analyzed. The optimization methods for sizing sleep transistors of power-gating circuits are addressed in terms of energy dissipations. The design methods of the power-gating SRMCML circuits are presented. The effectiveness of the proposed power-gating structure is verified by using HSPICE simulations with a SMIC 130nm technology. From the outcomes of simulations, the energy loss of the power-gating SRMCML circuits is smaller than corresponding static CMOS alternatives in high frequencies.