scholarly journals Analog based Neuromorphic Systems on Low Power Current Mode Circuits

Neuromorphic computing is the process used to appliance the neural system models. Formerly, it is referred to as the biological process and later it turned out to be the computing algorithms. Many neuromorphic algorithms represented as the neural figures such as neural spikes, fluctuated graphs, and synapses. The biological nervous system for instance consists of huge number of neurons and they collectively work to encode the stimulus of various senses. In case of neuromorphic computing, automated brain brings in the concept of efficient work carried out through artificial means. The neuromorphic computing thus evolves as a major technological advancement and the need of such technique is the need of the hour in various scientific as well as field applications. In existing techniques, the scaling, power and area are not efficient. This study attempts to address the major issues such as scaling and power. This paper explains the design on a non-spiking network which is used for population coding architecture. The model which is discussed in this paper is based on the analog domain and the current mode circuits are also involved. The input neuron model consists of current direction selector block, current scale block and minimum current block which all comprise to form the neuron model. This paper also brings out the possible outcome of low power constraints. This paper involves 180nm technology with which the power is measured. This paper brings out the simulations of both 180 and 90nm technologies. Apart from current scale block, minimum current block and current direction selector block, there are other blocks such as current splitter block and current mode low pass filter block, where all the circuits work under the sub-threshold condition. The power consumption obtained in the 180 nm technology is 58.838 µW and its energy equivalent is 1.765pJ. Neuromorphic computing is used as an application where the machines are being automated and such machines come with self-thinking capability. Neuromorphic computing design which is evolved from this paper is found to be more power ad energy efficient. The tool used is Cadence Virtuoso.

Author(s):  
MOHAMMAD HADI DANESH ◽  
SASAN NIKSERESHT ◽  
MAHYAR DEHDAST

In this paper a low-power current-mode RMS-to-DC converter is proposed. The proposed converter includes absolute value circuit, squarer/divider circuit, low-pass filter and square root circuit which employ CMOS transistors operating in weak inversion region. The RMS-to-DC converter has low power consumption (<1μW), low supply voltage (0.9V), wide input range (from 50 nA to 500 nA), low relative error (<3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.


Author(s):  
MOHAMMAD HADI DANESH ◽  
MAHYAR DEHDAST ◽  
ABDOLGHANI AREKHI ◽  
AMIN EMAMI FARD

In this paper a low-power current-mode RMS-to-DC converter is proposed. The converter includes two-quadrant squarer/divider and the first-order low-pass filter cell, both of them use MOS translinear loops. The RMS-to-DC converter has low power consumption (< 0.75μW), low supply voltage (0.8 V), wide input range (from 40 nA to 500 nA), low relative error (< 3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.


2015 ◽  
Vol 124 (11) ◽  
pp. 1-4
Author(s):  
Rahul Kumar ◽  
D.K. Raghuvanshi ◽  
Jaykant Dangi

2016 ◽  
Vol 26 (03) ◽  
pp. 1750048 ◽  
Author(s):  
Vida Orduee Niar ◽  
Gholamreza Zare Fatin

In this paper, a [Formula: see text]-[Formula: see text] low-pass and low power filter with tunable in-band attenuation for WiMAX/LTE receiver is presented. The fourth-order filter consists of two cascaded biquad stages. The source-follower (SF) stage is used as a key building block in these biquads. In this paper, we have presented a circuit technique to reduce the nonlinearity of the SF stage resulting from unmatched signal swings at the gate and source terminals of the input transistor. The proposed SF stage, is used for design of a linear biquad which is then utilized in a fourth-order Butterworth low-pass filter. The simulation results of the filter for bandwidth of 10 MHz show that the IIP3 of the filter is equal to 8.22[Formula: see text]dBm, in-band noise density is 100[Formula: see text]nV/[Formula: see text]Hz and power consumption is 5.9[Formula: see text]mW. The supply voltage of the filter is equal to 1[Formula: see text]V.


2017 ◽  
Vol 13 (15) ◽  
pp. 170
Author(s):  
Haitham K. Ali ◽  
Jihan S. Abdaljabar

As the transistors are continuously scaling down, it becomes necessary to reduce voltage supply and power requirements of the circuit to increase its performance and stability. Whereas, current- mode devices require less number of stages with high output impedance results in improved performance and large bandwidth as compared to voltage-mode techniques. OTA are current-mode device that takes voltage as input and produces current as output with high gain and large bandwidth. The frequency bands were parameters were determined such as the cutoff frequency (fc), the band width (BW), the quality factor (Q), and the angular frequency (Wo). In this paper the design and the simulation of the transfer function has been done by using (MATLAB) in order to obtain the frequency response for all types of filter (the low pass filter, high pass filter, band pass filter and band stop filter).


2011 ◽  
Vol 32 (9) ◽  
pp. 095002 ◽  
Author(s):  
Zheng Gong ◽  
Bei Chen ◽  
Xueqing Hu ◽  
Yin Shi ◽  
Fa Foster Dai

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