Design of a Capacitorless Dynamic Random Access Memory Based on Ultra-Thin Polycrystalline Silicon Junctionless Field-Effect Transistor with Dual-Gate

In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with an ultrathin polycrystalline silicon layer was designed and investigated by using technology computer-aided design simulation (TCAD). The application of a negative voltage at the control gate results in the generation of holes in the storage region by the band-to-band tunneling (BTBT) effect. Memory characteristics such as sensing margin and retention time are affected by the doping concentration of the storage region, bias condition of the program, and length of the intrinsic region. In addition, the gate acts as a switch that controls the transfer characteristics while the control gate plays a role in retaining holes in the hold state. The device was optimized, considering various parameters such as the doping concentration of the storage region (Nstorage), intrinsic region length (Lint), and operation bias conditions to obtain a high sensing margin of 49.7 μA/μm and a long retention time of 2 s even at a high temperature of 358 K. The obtained retention time is almost 30 times longer than that predicted for modern DRAM cells by the International technology roadmap for semiconductors (ITRS).

Effects of Parasitic Region in SiC Bipolar Junction Transistors on Forced Current Gain

Effects of a parasitic region in SiC BJTs on conductivity modulation and a forced current gain (βF) were investigated by using TCAD simulation with various device structures. By introducing an Al+-implanted region below the base parasitic region, βF can be improved because the implanted region can reduce the base spreading resistance, leading to alleviation of debiasing effect. βF in devices with various parasitic areas, whose base spreading resistances were reduced by the Al+-implantation, were compared. We found that βF can be enhanced by expanding the parasitic area if the base spreading resistance is sufficiently reduced. The higher βF is attributed to an expanded conductivity-modulated region. The collector current spreading in the collector layer and the hole injection from the parasitic region as well as from the intrinsic region can play a role to evoke the conductivity modulation. Thus, the larger parasitic region can expand the conductivity-modulated region, resulting in expansion of an active area and the enhancement of βF.

Ion Implanted Lateral p+-i-n+ Diodes on HPSI 4H-SiC

Square shaped annular lateral p+–i–n+ diodes on high purity semi-insulating (HPSI) 4H-SiC are fabricated by Al+ and P+ ion implantation to obtain anode and cathode regions, respectively. All the diodes have the same size central anode surrounded by an intrinsic region, which is surrounded by an annular cathode. Anode area and annular cathode width are fixed for all diodes, only the lateral length of the intrinsic region is varied. Post implantation annealing is performed at 1950 °C for 10 min. Static forward and reverse characteristics are measured in the temperature range of 30 - 290 °C. For all diodes, the reverse current is below the instrument detection limit of 10-14 A up to 100 °C at 200 V, the maximum reverse bias employed in this study. The reverse current increased up to low 108 A for 200 V reverse bias at 290 °C. Forward currents overlap at the low voltage region once they exceed the instrument detection limit at ~1.6 V and 30 °C. The forward currents follow almost identical exponential trend at all measured temperatures while the diode series resistance increase with increasing anode-cathode distance and decreased with increasing temperature for the given intrinsic region lateral length.