Design of a Capacitorless Dynamic Random Access Memory Based on Ultra-Thin Polycrystalline Silicon Junctionless Field-Effect Transistor with Dual-Gate

2021 ◽  
Vol 21 (8) ◽  
pp. 4223-4229
Author(s):  
Sang Ho Lee ◽  
Min Su Cho ◽  
Jun Hyeok Jung ◽  
Won Douk Jang ◽  
Hye Jin Mun ◽  
...  
Keyword(s):  
Retention Time ◽  
Computer Aided Design ◽  
Polycrystalline Silicon ◽  
Field Effect ◽  
Doping Concentration ◽  
Field Effect Transistor ◽  
Silicon Layer ◽  
Intrinsic Region ◽  
Storage Region ◽  
Effect Transistor

In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with an ultrathin polycrystalline silicon layer was designed and investigated by using technology computer-aided design simulation (TCAD). The application of a negative voltage at the control gate results in the generation of holes in the storage region by the band-to-band tunneling (BTBT) effect. Memory characteristics such as sensing margin and retention time are affected by the doping concentration of the storage region, bias condition of the program, and length of the intrinsic region. In addition, the gate acts as a switch that controls the transfer characteristics while the control gate plays a role in retaining holes in the hold state. The device was optimized, considering various parameters such as the doping concentration of the storage region (Nstorage), intrinsic region length (Lint), and operation bias conditions to obtain a high sensing margin of 49.7 μA/μm and a long retention time of 2 s even at a high temperature of 358 K. The obtained retention time is almost 30 times longer than that predicted for modern DRAM cells by the International technology roadmap for semiconductors (ITRS).

Temperature Sensitivity Analysis of Extended Source Double Gate Tunnel Field Effect Transistor

2021 ◽  
Author(s):  
Dharmender Nishad ◽  
Kaushal Nigam ◽  
Satyendra Kumar
Keyword(s):  
Temperature Sensitivity ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Of Temperature ◽  
Double Gate ◽  
Extended Source ◽  
Temperature Variations ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract Temperature-induced performance variation is one of the main concerns of the conventional stack gate oxide double gate tunnel field-effect transistor (SGO-DG-TFET). In this regard, we investigate the temperature sensitivity of extended source double gate tunnel field-effect transistor (ESDG-TFET). For this, we have analyzed the effect of temperature variations on the transfer characteristics, analog/RF, linearity and distortion figure of merits (FOMs) using technology computer aided design (TCAD) simulations. Further, the temperature sensitivity performance is compared with conventional SGO-DG-TFET. The comparative analysis shows that ESDG-TFET is less sensitive to temperature variations compared to the conventional SGO-DG-TFET. Therefore, this indicates that ESDG-TFET is more reliable for low-power, high-frequency applications at a higher temperature compared to conventional SGO-DG-TFET.

scholarly journals Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 30 ◽  
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Garam Kim ◽  
Sangwan Kim ◽  
Byung-Gook Park
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Performance ◽  
Control Group ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
High Level ◽  
Aided Design

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.

scholarly journals Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

2021 ◽  
Author(s):  
Garima Jain ◽  
Ravinder Singh Sawhney ◽  
Ravinder Kumar ◽  
Amit Saini
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Subthreshold Swing ◽  
Short Channel ◽  
Tunneling Mechanism ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12nm with Contact poly pitch (CPP) of 48nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10-16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 1011 has been achieved. The device exhibits a high transconductance of 3.022x10-5 S at the gate to source voltage of 1V. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

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