Resistive Switching in CdTe/CdSe Core–Shell Quantum Dots Embedded Chitosan-Based Memory Devices

In this paper, we report on the resistive switching (RS) and conduction mechanisms in devices consisting of CdTe/CdSe core–shell quantum dots embedded chitosan composites active layer. Two devices with active layers sandwiched between (1) Al and Ag, and (2) ITO and Ag electrodes were studied. Both devices exhibited bipolar memory behavior with [Formula: see text] V and [Formula: see text][Formula: see text]V, for the Al-based device, while [Formula: see text] V and [Formula: see text][Formula: see text]V were observed for the ITO-based device, enabling both devices to be operated at low powers. However, the switching mechanisms of both devices were different, i.e., RS in Al device was attributed to conductive bridge mechanism, while space-charge-limited driven conduction filament attributed the switching mechanism of the ITO device. Additionally, the Al-based device showed long retention ([Formula: see text][Formula: see text]s) and a reasonable large ([Formula: see text]) ON/OFF ratio. Additionally, for this device, we also observed sweeping cycle-induced reversal of voltage polarity of the [Formula: see text] and [Formula: see text]. In contrast, we observed that increasing sweeping cycles resulted in an exponential decrease of the OFF-state resistance of the ITO-based device.

Transition from nonvolatile bipolar memory switching to bidirectional threshold switching in layered MoO3 nanobelts

The transition from bipolar memory switching to bidirectional threshold switching in layered MoO3 nanobelts via changing electrodes from Au to Ag.

Silicon Nanocrystalline Nonvolatile Memory - Characterization and Analysis

In this work, nanocrystal nonvolatile memory devices comprising of silicon nanocrystals located in gate oxide of MOS structure, were comprehensively studied on specialized modular data acquisition setup developed for capacitance-voltage measurements. The memory window formation, memory window retention and charge relaxation experimental methods were used to study the trapping/emission processes inside the dielectric layer of MOS capacitor memory. The trapping/emission processes were studied in standard bipolar memory mode and in new unipolar memory mode, which is specific for nanocrystalline nonvolatile memory. The analysis of experimental results shown that unipolar programming mode is more favourable for nanocrystalline memory operation due to lower wearing out and higher breakdown immunity of the MOS device’s oxide. The study was performed for two types of nanocrystalline memory devices: with one and two silicon nanocrystalline 2D layers in oxide of MOS structure correspondingly. The electrostatic modelling was presented to explain the experimental results.