Detailed Placement and Global Routing Co-optimization with Complex Constraints

With several divided stages, placement and routing are the most critical and challenging steps in VLSI physical design. To ensure that physical implementation problems can be manageable and converged in a reasonable runtime, placement/routing problems are usually further split into several sub-problems, which may cause conservative margin reservation and mis-correlation. Therefore, it is desirable to design an algorithm that can accurately and efficiently consider placement and routing simultaneously. In this paper, we propose a detailed placement and global routing co-optimization algorithm while considering complex routing constraints to avoid conservative margin reservation and mis-correlation in placement/routing stages. Firstly, we present a rapidly preprocessing technology based on R-tree to improve the initial routing results. After that, a BFS-based approximate optimal addressing algorithm in 3D is designed to find a proper destination for cell movement. We propose an optimal region selection algorithm based on the partial routing solution to jump out of the local optimal solution. Further, a fast partial net rip-up and rerouted algorithm is used in the process of cell movement. Finally, we adopt an efficient refinement technique to reduce the routing length further. Compared with the top 3 winners according to the 2020 ICCAD CAD contest benchmarks, the experimental results show that our algorithm achieves the best routing length reduction for all cases with a shorter runtime. On average, our algorithm can improve 0.7%, 1.5%, and 1.7% for the first, second, and third place, respectively. In addition, we can still obtain the best results after relaxing the maximum cell movement constraint, which further illustrates the effectiveness of our algorithm.

Pair Wise Swapping Based Hypergraph Partitioning Algorithms for VLSI Design

A VLSI integrated circuit is the most significant part of electronic systems such as personal computer or workstation, digital camera, cell phone or a portable computing device, and automobile. So development within the field of electronic space depends on the design planning of VLSI integrated circuit. Circuit partitioning is most important step in VLSI physical design process. Many heuristic partitioning algorithms are proposed for this problem. The first heuristic algorithm for hypergraph partitioning in the domain of VLSI is FM algorithm. In this paper, I have proposed three variations of FM algorithm by utilizing pair insightful swapping strategies. I have played out a relative investigation of FM and my proposed algorithms utilizing two datasets for example ISPD98 and ISPD99. Test results demonstrate that my proposed calculations outflank the FM algorithm.

Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology

Rectilinear Steiner Tree (RST) construction is a fundamental problem in very large scale integration (VLSI) physical design. Its applications include placement and routing in VLSI physical design automation (PDA) where wire length and timing estimations for signal nets are obtained. In this paper, a pseudo-Boolean satisfiability (PB-SAT)-based approach is presented to solve rectilinear Steiner tree problem. But large nets are a bottleneck for any SAT-based approach. Hence, to deal with large nets, a region-partitioning-based algorithm is taken into consideration, which eventually achieves a reasonable running time. Furthermore, a clustering-based approach is also explored to improve the partitioning of nets by identifying clusters and then applying a heuristic-based approach to get the minimum wire length for each set of the clusters. Experimental results obtained by these techniques show that the proposed algorithm can solve the RST problem very effectively even on large circuits and it outperforms the widely used RST algorithm FLUTE with 3[Formula: see text][Formula: see text][Formula: see text]to 9[Formula: see text][Formula: see text][Formula: see text]speedups.