scholarly journals Reconfigurable Morphological Processor for Grayscale Image Processing

Electronics ◽  
2021 ◽  
Vol 10 (19) ◽  
pp. 2429
Author(s):  
Bin Zhang
Keyword(s):  
Image Processing ◽  
Embedded Systems ◽  
High Performance ◽  
Morphological Processing ◽  
Process Synthesis ◽  
Morphological Operations ◽  
Grayscale Image ◽  
Reconfigurable Processor ◽  
System Clock ◽  
Processing Module

Grayscale morphology is a powerful tool in image, video, and visual applications. A reconfigurable processor is proposed for grayscale image morphological processing. The architecture of the processor is a combination of a reconfigurable grayscale processing module (RGPM) and peripheral circuits. The RGPM, which consists of four grayscale computing units, conducts grayscale morphological operations and implements related algorithms of more than 100 f/s for a 1024 × 1024 image. The periphery circuits control the entire image processing and dynamic reconfiguration process. Synthesis results show that the proposed processor can provide 43.12 GOPS and achieve 8.87 GOPS/mm2 at a 220-MHz system clock. The simulation and experimental results show that the processor is suitable for high-performance embedded systems.

Panoramic Vision System for Autonomous Driving Vehicle

2014 ◽  
Vol 644-650 ◽  
pp. 497-501
Author(s):  
Yu Bin Zhou
Keyword(s):  
Image Processing ◽  
High Performance ◽  
Vision System ◽  
Autonomous Driving ◽  
Intelligent Vehicles ◽  
Lane Detection ◽  
Detection And Tracking ◽  
Panoramic Vision ◽  
Processing Module ◽  
Time Image

High effective vision system is important for autonomous driving vehicles. A panoramic vision system based on FPGA+DSP with 6-camera for intelligent vehicles is presented in this paper. The system includes digital image acquisition module and high image processing module which work independently to each other. The including two C6416 DSP chips and one high-performance Virtex-4 FPGA to achieve the complex real-time image processing during autonomous driving, such as cylindrical panoramic image rebuilding, lane detection and tracking. The proposed algorithm was also optimized according to the specific characteristics of the hardware for high parallel processing in FPGA and pipelined in DSP.

Matlab and Parallel Computing

2012 ◽  
Vol 17 (4) ◽  
pp. 207-216 ◽  
Author(s):  
Magdalena Szymczyk ◽  
Piotr Szymczyk
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Parallel Computing ◽  
Distributed Computing ◽  
Control Systems ◽  
High Performance ◽  
Parallel Applications ◽  
Process Simulations ◽  
Key Features ◽  
Financial Process

Abstract The MATLAB is a technical computing language used in a variety of fields, such as control systems, image and signal processing, visualization, financial process simulations in an easy-to-use environment. MATLAB offers "toolboxes" which are specialized libraries for variety scientific domains, and a simplified interface to high-performance libraries (LAPACK, BLAS, FFTW too). Now MATLAB is enriched by the possibility of parallel computing with the Parallel Computing ToolboxTM and MATLAB Distributed Computing ServerTM. In this article we present some of the key features of MATLAB parallel applications focused on using GPU processors for image processing.

A High Performance Image Processing Unit for On-orbit Servicing

2006 ◽  
Author(s):  
Hiroshi Yamamoto ◽  
Yasufumi Nagai ◽  
Shinichi Kimura ◽  
Hiroshi Takahashi ◽  
Satoko Mizumoto ◽  
...  
Keyword(s):  
Image Processing ◽  
High Performance ◽  
Processing Unit

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing

2013 ◽  
Vol 21 (3) ◽  
pp. 552-562
Author(s):  
Hsuan-Chun Liao ◽  
Mochamad Asri ◽  
Tsuyoshi Isshiki ◽  
Dongju Li ◽  
Hiroaki Kunieda
Keyword(s):  
Image Processing ◽  
High Performance ◽  
Two Dimensional ◽  
Dimensional Image ◽  
Two Dimensional Image

Micro-Flow-Cytometer Integrated witch Optical Tweezer and DIP Technique for Cell/Particle Sorting and Manipulation

2007 ◽  
Vol 121-123 ◽  
pp. 1351-1354
Author(s):  
Yu Sheng Chien ◽  
Che Hsin Lin ◽  
Fu Jen Kao ◽  
Cheng Wen Ko
Keyword(s):  
Image Processing ◽  
Digital Image Processing ◽  
Digital Image ◽  
High Performance ◽  
Optical Tweezer ◽  
Processing Technique ◽  
Microfluidic System ◽  
Image Processing Technique ◽  
Target Cells ◽  
Digital Image Processing Technique

This paper proposes a novel microfluidic system for cell/microparticle recognition and manipulation utilizing digital image processing technique (DIP) and optical tweezer under microfluidic configuration. Digital image processing technique is used to count and recognize the cell/particle samples and then sends a control signal to generate a laser pulse to manipulate the target cell/particle optically. The optical tweezer system is capable of catching, moving and switching the target cells at the downstream of the microchannel. The trapping force of the optical tweezer is also demonstrated utilizing Stocks-drag method and electroosmotic flow. The proposed system provides a simple but high-performance solution for microparticle manipulation in a microfluidic device.

Massive Image Treatment System Based on Cloud Computing Platform

2014 ◽  
Vol 687-691 ◽  
pp. 3733-3737
Author(s):  
Dan Wu ◽  
Ming Quan Zhou ◽  
Rong Fang Bie
Keyword(s):  
Image Processing ◽  
Cloud Computing ◽  
High Performance ◽  
Large Scale ◽  
Processing System ◽  
Virtual Space ◽  
Image Processing System ◽  
Computing Platform ◽  
Simulation Calculation ◽  
Computer Resources

Massive image processing technology requires high requirements of processor and memory, and it needs to adopt high performance of processor and the large capacity memory. While the single or single core processing and traditional memory can’t satisfy the need of image processing. This paper introduces the cloud computing function into the massive image processing system. Through the cloud computing function it expands the virtual space of the system, saves computer resources and improves the efficiency of image processing. The system processor uses multi-core DSP parallel processor, and develops visualization parameter setting window and output results using VC software settings. Through simulation calculation we get the image processing speed curve and the system image adaptive curve. It provides the technical reference for the design of large-scale image processing system.

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