Hardware description of a simplified 4-bit softcore processor with BCD capabilities

The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching as computers architecture subject as digital circuits subject in the technology faculty of the Universidad Distrital. The new features include arithmetic instruction with input carry, BCD operations enabling, rotating instructions, implementation of input and output register banks, increase of the number of general purpose registers of the data memory, and the reduction of the execution clock cycles per instruction. Additionally, the assembler software was enabled to support macro-instructions to make easy the comprehension of some composed functions. As result, a very compact softcore processor was obtained, by means of a Verilog description done in a single file. This implementation occupies only the 2% of the medium-size FPGA used for the application, reaching a maximum possible working clock frequency of 929 Mhz.

Research and Capstone Project Electronic Repository

Aims: Higher Education Institutions are challenged to manage research and capstone projects output available through open access is something that is increasingly mandated by funders and universities in many countries. Study Design: This is to widen the dissemination of results to the community which information technology practices and theory can address. Place and Duration of Study: This project tries to investigate the possible outcomes by developing an online repository for research and capstone project in Southern Philippines Agri-Business and Marine and Aquatic School of Technology that can deposit students output, register various accounts, log transactions and an interactive website. Methodology: Innovative research approach is being manifested in the development that uses modified waterfall, white-box testing and survey-type methodologies are being highlighted. Results: The website is successfully developed with specific functionality on referencing, data storage, data security, data extraction and some special functionalities. The fifty evaluators gave very agreeable results to the reliability, functionality and usability of the website. Conclusion: Although, the system is functional and evaluated very agreeable to the respondents the testing is very crucial that proper monitoring should be in place in the entire plan.

Output Register Parallelism in an Identical Direct and Semi-Direct Speaking Test

The present trend in developing and using semi-direct speaking tests has been supported by test developers and researchers' claim of their increased practicality, higher reliability and concurrent validity with test scores in direct oral proficiency interviews. However, it is universally agreed within the language testing and assessment community that interchangeability must be investigated from multiple perspectives. This study compared test taker output from a computer-based Aptis General speaking test and a purposively developed identical face-to-face direct oral proficiency interview using a counterbalanced research design. Within subject analyses of salient output features identified in prior related research were completed. Results showed that test taker output in the computer-based test was less contextualised, with minimally higher lexical density and syntactic complexity. Given these findings, the indicated slight register shift in output may be viewed as non-consequential, or even as advantageous, for semi-direct speaking tests.

QUANTUM TIMING AND SYNCHRONIZATION PROBLEMS

Feynman's model of a quantum computer provides an example of a continuous-time quantum walk. Its clocking mechanism is an excitation of a basically linear chain of spins with occasional controlled jumps which allow for motion on a planar graph. The spreading of the wave packet poses limitations on the probability of ever completing the s elementary steps of a computation: an additional amount of storage space δ is needed in order to achieve an assigned completion probability. In this note we study the END instruction, viewed as a measurement of the position of the clocking excitation: a π-pulse indefinitely freezes the contents of the input/output register, with a probability depending only on the ratio δ/s.