Network-on-a-chip of a new microprocessor generation with the Elbrus architecture

The paper describes a network-on-chip of a new microprocessor generation with the Elbrus architecture, taking into account the peculiarities of physical design. The network-on-a-chip under consideration plays a central role in the scaling process of the microprocessor, interconnecting all the main components of the system and ensuring the transfer of all types of packets between devices. The characteristics of the network-on-a-chip determine the bandwidth and access time to the memory subsystem.