Novel VDBA based universal filter topologies with minimum passive components

In this research, voltage differencing buffered amplifier (VDBA) is utilized in designing three novel multi-input single output (MISO) topologies of universal filters. The designed filters employ minimum number of passive components and did not require any passive component matching condition. Two of the designed filters can work in dual mode of operation simultaneously. The designed filters have inbuilt tunability property. The nonideal gain analysis and sensitivity analysis of the filters are also carried out to study the effect of process variations and process spread on the filter responses. The complete layout of the VDBA is designed using 0.18μm Silterra Malaysia process design kit (PDK) in Cadence design software. The parasitic extraction is done using Mentor graphics Calibre tool. The postlayout simulations bear close resemblance with the theoretical predictions.

Face Recognition on a Smart Image Sensor Using Local Gradients

In this paper, we present the architecture of a smart imaging sensor (SIS) for face recognition, based on a custom-design smart pixel capable of computing local spatial gradients in the analog domain, and a digital coprocessor that performs image classification. The SIS uses spatial gradients to compute a lightweight version of local binary patterns (LBP), which we term ringed LBP (RLBP). Our face recognition method, which is based on Ahonen’s algorithm, operates in three stages: (1) it extracts local image features using RLBP, (2) it computes a feature vector using RLBP histograms, (3) it projects the vector onto a subspace that maximizes class separation and classifies the image using a nearest neighbor criterion. We designed the smart pixel using the TSMC 0.35 μm mixed-signal CMOS process, and evaluated its performance using postlayout parasitic extraction. We also designed and implemented the digital coprocessor on a Xilinx XC7Z020 field-programmable gate array. The smart pixel achieves a fill factor of 34% on the 0.35 μm process and 76% on a 0.18 μm process with 32 μm × 32 μm pixels. The pixel array operates at up to 556 frames per second. The digital coprocessor achieves 96.5% classification accuracy on a database of infrared face images, can classify a 150×80-pixel image in 94 μs, and consumes 71 mW of power.

An RF Approach to Modelling Gallium Nitride Power Devices Using Parasitic Extraction

This paper begins with a comprehensive review into the existing GaN device models. Secondly, it identifies the need for a more accurate GaN switching model. A simple practical process based on radio frequency techniques using Vector Network Analyser is introduced in this paper as an original contribution. It was applied to extract the impedances of the GaN device to develop an efficient behavioural model. The switching behaviour of the model was validated using both simulation and real time double pulse test experiments at 500 V, 15 A conditions. The proposed model is much easier for power designers to handle, without the need for knowledge about the physics or geometry of the device. The proposed model for Transphorm GaN HEMT was found to be 95.2% more accurate when compared to the existing LT-Spice manufacturer model. This work additionally highlights the need to adopt established RF techniques into power electronics to reduce the learning curve while dealing with these novel high-speed switching devices.

Multi-Core Eight Bit Ternary Content-Addressable Memory Design Based Image Learning System

In this research work, the image is learned to find features to make use of during its analysis and a genetic apices based low power Ternary Content-Addressable Memory (TCAM) is designed to implement the proposed image learning system. A technique called Content Matching Search Register is proposed in this work to perform the image learning operations in proposed TCAM architecture. This paper proposes an ImOFF algorithm for image analysis. The focus of this multi-core TCAM (MC-TCAM) is to make fast computations and search based designs. The focus application of this research work is in the design of low power On-board Embedded-VLSI chip to perform image analysis. Proposed multi-core eight bit Ternary TCAM (MCEB-TCAM) is analyzed using IC design tools in 90nm technology, using Verilog hardware description language and usage of Cadence for layout generation and parasitic extraction of the circuit components.