VERTEX SPLITTING IN DAGS AND APPLICATIONS TO PARTIAL SCAN DESIGNS AND LOSSY CIRCUITS

Directed acyclic graphs (dags) are often used to model circuits. Path lengths in such dags represent circuit delays. In the vertex splitting problem, the objective is to determine a minimum number of vertices to split so that the resulting dag has no path of length > δ. This problem has application to the placement of flip-flops in partial scan designs, placement of latches in pipelined circuits, placement of signal boosters in lossy circuits and networks, etc. Several simplified versions of this problem are shown to be NP-hard. A linear time algorithm is obtained for the case when the dag is a tree. A backtracking algorithm and heuristics are developed for general dags and experimental results using dags obtained from ISCAS benchmark circuits are obtained.

Process Design & Integration of Salicide and Source/Drain Process Modules for Improved Device Performance

ABSTRACTIn integrated circuit (IC) fabrication, understanding and optimizing process interactions and variability is critical for swift process integration and performance enhancement, especially at dimensions ≤0.25μm. We present here an approach to address this challenge, and we apply it to improve the process design for two critical modules in a typical CMOS IC process—salicide and source/drain. Together, these modules impact the silicide-to-diffusion contact resistance (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. In our approach, we have investigated a process domain consisting of both silicide and source/drain process variables; and we have developed a quantitative framework for analysis and optimization, along with qualitative insight into underlying the physical mechanisms. We demonstrate that the transistor drive current (Id) improves by ≈5‥, and circuit performance, as measured by the figure-of-merit (FOM), by ≈4‥. This improvement is significant, and an added benefit is that other transistor characteristics such as effective channel length, off-current, substrate current etc. are affected minimally. Finally, we use this approach to optimize trade-offs such as Rc vs Rs and performance vs manufacturability; thus enabling manufacturable processes that meet the requirements for high performance.

Process Design & Integration of Salicide and Source/Drain process Modules for Improved Device Performance

ABSTRACTTo enable swift integration of process modules into manufacturable process flows; three components – individual process modules, their interactions and their variability-must be understood well. At dimensions ≤ 0.25 μm, this understanding is especially critical, and also quite challenging. We present here an approach to address this challenge by joint process design, using two key modules-salicide and source/drain-as an example. Together, these modules impact the silicide-to-diffusion contact resistance, (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. We have built a model to help provide insight into the underlying physical mechanisms, and to help provide a quantitative framework for optimizing performance and variability. Rc, depends critically on the doping concentration immediately adjacent to the silicide, and this concentration is determined by the combined effect of silicide processing and the two-dimensional source/drain dopant profile. Rs depends on the thickness and phase of the silicide film formed, which, in turn, depend on the salicide process variables as well as the source/drain doping concentration, because both affect the silicide growth kinetics. Process conditions favoring Rs. and Rc are opposite to each other: thicker silicide films and higher thermal budgets help in the phase-transformation to the low-resistivity C54 phase and improve Rs but they increase dopant redistribution and worsen Rc. Optimal process design can improve the transistor drive current (Id) by ≈5%, and circuit performance, as measured by the figure-of-merit (FOM) by ≈ 4%. This improvement is significant, and an added benefit of this approach is that other transistor characteristics such as effective channel length, off-current, substrate current, etc. remain unchanged. In summary, we have demonstrated that by joint process design and integration of the salicide and source/drain modules, insight can be gained into the underlying physical mechanisms, and device and circuit performance can be improved significantly.