Process Design & Integration of Salicide and Source/Drain Process Modules for Improved Device Performance

1998 ◽  
Vol 525 ◽  
Author(s):  
Pushkar P. Apte ◽  
Sharad Saxena ◽  
Suraj Rao ◽  
Karthik Vasanth ◽  
Douglas A. Prinslow ◽  
...  
Keyword(s):  
Process Design ◽  
Integrated Circuit ◽  
High Performance ◽  
Performance Enhancement ◽  
Process Integration ◽  
Channel Length ◽  
Trade Offs ◽  
Design Integration ◽  
And Performance ◽  
Circuit Delays

ABSTRACTIn integrated circuit (IC) fabrication, understanding and optimizing process interactions and variability is critical for swift process integration and performance enhancement, especially at dimensions ≤0.25μm. We present here an approach to address this challenge, and we apply it to improve the process design for two critical modules in a typical CMOS IC process—salicide and source/drain. Together, these modules impact the silicide-to-diffusion contact resistance (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. In our approach, we have investigated a process domain consisting of both silicide and source/drain process variables; and we have developed a quantitative framework for analysis and optimization, along with qualitative insight into underlying the physical mechanisms. We demonstrate that the transistor drive current (Id) improves by ≈5‥, and circuit performance, as measured by the figure-of-merit (FOM), by ≈4‥. This improvement is significant, and an added benefit is that other transistor characteristics such as effective channel length, off-current, substrate current etc. are affected minimally. Finally, we use this approach to optimize trade-offs such as Rc vs Rs and performance vs manufacturability; thus enabling manufacturable processes that meet the requirements for high performance.

Process Design & Integration of Salicide and Source/Drain process Modules for Improved Device Performance

1998 ◽  
Vol 514 ◽  
Author(s):  
Pushkar P. Apte ◽  
Shared Saxena ◽  
Suraj Rao ◽  
Karthik Vasanth ◽  
Douglas A. Prinslow ◽  
...  
Keyword(s):  
Process Design ◽  
Doping Concentration ◽  
Channel Length ◽  
Process Conditions ◽  
Circuit Performance ◽  
Physical Mechanisms ◽  
Substrate Current ◽  
Design Integration ◽  
Circuit Delays ◽  
Dopant Redistribution

ABSTRACTTo enable swift integration of process modules into manufacturable process flows; three components – individual process modules, their interactions and their variability-must be understood well. At dimensions ≤ 0.25 μm, this understanding is especially critical, and also quite challenging. We present here an approach to address this challenge by joint process design, using two key modules-salicide and source/drain-as an example. Together, these modules impact the silicide-to-diffusion contact resistance, (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. We have built a model to help provide insight into the underlying physical mechanisms, and to help provide a quantitative framework for optimizing performance and variability. Rc, depends critically on the doping concentration immediately adjacent to the silicide, and this concentration is determined by the combined effect of silicide processing and the two-dimensional source/drain dopant profile. Rs depends on the thickness and phase of the silicide film formed, which, in turn, depend on the salicide process variables as well as the source/drain doping concentration, because both affect the silicide growth kinetics. Process conditions favoring Rs. and Rc are opposite to each other: thicker silicide films and higher thermal budgets help in the phase-transformation to the low-resistivity C54 phase and improve Rs but they increase dopant redistribution and worsen Rc. Optimal process design can improve the transistor drive current (Id) by ≈5%, and circuit performance, as measured by the figure-of-merit (FOM) by ≈ 4%. This improvement is significant, and an added benefit of this approach is that other transistor characteristics such as effective channel length, off-current, substrate current, etc. remain unchanged. In summary, we have demonstrated that by joint process design and integration of the salicide and source/drain modules, insight can be gained into the underlying physical mechanisms, and device and circuit performance can be improved significantly.

High-Performance Image Filters via Sparse Approximations

2020 ◽  
Vol 3 (2) ◽  
pp. 1-19
Author(s):  
Kersten Schuster ◽  
Philip Trettner ◽  
Leif Kobbelt
Keyword(s):  
High Performance ◽  
Hardware Acceleration ◽  
Optimization Method ◽  
Translation Invariant ◽  
Approximation Quality ◽  
Trade Offs ◽  
Sparse Approximations ◽  
Image Filters ◽  
Good Trade ◽  
And Performance

We present a numerical optimization method to find highly efficient (sparse) approximations for convolutional image filters. Using a modified parallel tempering approach, we solve a constrained optimization that maximizes approximation quality while strictly staying within a user-prescribed performance budget. The results are multi-pass filters where each pass computes a weighted sum of bilinearly interpolated sparse image samples, exploiting hardware acceleration on the GPU. We systematically decompose the target filter into a series of sparse convolutions, trying to find good trade-offs between approximation quality and performance. Since our sparse filters are linear and translation-invariant, they do not exhibit the aliasing and temporal coherence issues that often appear in filters working on image pyramids. We show several applications, ranging from simple Gaussian or box blurs to the emulation of sophisticated Bokeh effects with user-provided masks. Our filters achieve high performance as well as high quality, often providing significant speed-up at acceptable quality even for separable filters. The optimized filters can be baked into shaders and used as a drop-in replacement for filtering tasks in image processing or rendering pipelines.

Fluorine plasma treatment on carbon-based perovskite solar cells for rapid moisture protection layer formation and performance enhancement

2020 ◽  
Vol 56 (4) ◽  
pp. 535-538 ◽  
Author(s):  
Jungwon Kim ◽  
Gyeongseop Lee ◽  
Kisu Lee ◽  
Haejun Yu ◽  
Jong Woo Lee ◽  
...  
Keyword(s):  
High Performance ◽  
Performance Enhancement ◽  
Perovskite Solar Cells ◽  
Perovskite Solar Cell ◽  
Layer Formation ◽  
Moisture Protection ◽  
Rapid Moisture ◽  
Protection Layer ◽  
And Performance ◽  
Treated Carbon

We first manufactured an F plasma-treated carbon electrode-based high performance perovskite solar cell with strong moisture resistance.

scholarly journals MG-RAST version 4—lessons learned from a decade of low-budget ultra-high-throughput metagenome analysis

2017 ◽  
Vol 20 (4) ◽  
pp. 1151-1159 ◽  
Author(s):  
Folker Meyer ◽  
Saurabh Bagchi ◽  
Somali Chaterji ◽  
Wolfgang Gerlach ◽  
Ananth Grama ◽  
...  
Keyword(s):  
Performance Optimization ◽  
High Performance ◽  
Lessons Learned ◽  
Added Value ◽  
Data Sets ◽  
Real World Data ◽  
Metagenome Analysis ◽  
Trade Offs ◽  
And Performance ◽  
The Right

Abstract As technologies change, MG-RAST is adapting. Newly available software is being included to improve accuracy and performance. As a computational service constantly running large volume scientific workflows, MG-RAST is the right location to perform benchmarking and implement algorithmic or platform improvements, in many cases involving trade-offs between specificity, sensitivity and run-time cost. The work in [Glass EM, Dribinsky Y, Yilmaz P, et al. ISME J 2014;8:1–3] is an example; we use existing well-studied data sets as gold standards representing different environments and different technologies to evaluate any changes to the pipeline. Currently, we use well-understood data sets in MG-RAST as platform for benchmarking. The use of artificial data sets for pipeline performance optimization has not added value, as these data sets are not presenting the same challenges as real-world data sets. In addition, the MG-RAST team welcomes suggestions for improvements of the workflow. We are currently working on versions 4.02 and 4.1, both of which contain significant input from the community and our partners that will enable double barcoding, stronger inferences supported by longer-read technologies, and will increase throughput while maintaining sensitivity by using Diamond and SortMeRNA. On the technical platform side, the MG-RAST team intends to support the Common Workflow Language as a standard to specify bioinformatics workflows, both to facilitate development and efficient high-performance implementation of the community’s data analysis tasks.

scholarly journals Giga-Scale Integration System-On-A-Chip Design: Challenges and Noteworthy Solutions

2020 ◽  
Vol 8 (6) ◽  
pp. 741-746
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Chip Design ◽  
Future Challenges ◽  
System On A Chip ◽  
And Performance ◽  
Exponential Rates ◽  
Scale Integration ◽  
Bus Architecture ◽  
Circuit Technology

In all respects of the last five decades, integrated circuit technology has advanced at exponential rates in both productivity and performance. Giga-Scale Integration (GSI) System-On-A-Chip (SoC) designs have become one of the main drivers of the integrated circuit technology in recent years. The objective of this work is to understand the challenges of Giga-scale SoC integration in nanometer technologies, and identify promising conveniences for innovation. Physical designs are crucial for SoC integration and in our work we identify them with details. In future the couplings and interactions among system components will increase as we put more of the system on a silicon die. Therefore the system designers will face challenges in several areas and we describe these future challenges briefly. Developing a design driver for GSI SoC design is important. With the help of this design driver we provide the design methodology, which ensures the high performance of the design. We present two noteworthy solutions which overcome the challenges of GSI SoC design. One is reuse and integration and another is efficient bus architecture. We also provide the challenges for verification of GSI SoC and methods to overcome these challenges.

Process Modeling and Integration of The Salicide Process Module for Sub-Half Micron Technology.

1995 ◽  
Vol 402 ◽  
Author(s):  
Pushkar P. Apte ◽  
Douglas A. Prinslow ◽  
Jorge A. Kittl ◽  
R. Scott list ◽  
Gordon Pollack
Keyword(s):  
Process Design ◽  
Integrated Circuit ◽  
Hierarchical Models ◽  
Technology Development ◽  
Cmos Technology ◽  
Technological Innovations ◽  
Capture Process ◽  
Significant Challenge ◽  
Metal Silicides ◽  
And Performance

AbstractMetal silicides have been used extensively in CMOS technology for reducing electrical resistance. As wafer-scale features have shrunk to the sub-half micron domain, obtaining a self-aligned silicide - or salicide - process that satisfies all requirements has become a significant challenge. One part of this challenge lies in developing the necessary scientific insights and technological innovations for the actual salicide process, while the other part lies in building a complete salicide process module which meets requirements of performance, reliability, ease of integration, control, etc. at the least possible cost and cycle-time for technology development. This second part is seldom addressed by researchers, and yet, is fundamentally important for successful application of any salicide technology to actual integrated circuit products. This paper presents a complete picture of the salicide module in the context of all the aforesaid components; and describes the use of abstraction and hierarchical models to capture process information and to facilitate process design. Prototype compact models for key wafer-state and performance outputs such as TiSi2 thickness and resistance are presented to demonstrate implementation of this process module.

scholarly journals Wavelength-division-multiplexing (WDM)-based integrated electronic–photonic switching network (EPSN) for high-speed data processing and transportation

Nanophotonics ◽  
2020 ◽  
Vol 9 (15) ◽  
pp. 4579-4588
Author(s):  
Chenghao Feng ◽  
Zhoufeng Ying ◽  
Zheng Zhao ◽  
Jiaqi Gu ◽  
David Z. Pan ◽  
...  
Keyword(s):  
Wavelength Division Multiplexing ◽  
High Speed ◽  
High Performance ◽  
Performance Enhancement ◽  
Switching Network ◽  
Photonic Switching ◽  
Wavelength Division ◽  
High Speed Data ◽  
And Performance ◽  
Performance Computing

AbstractIntegrated photonics offers attractive solutions for realizing combinational logic for high-performance computing. The integrated photonic chips can be further optimized using multiplexing techniques such as wavelength-division multiplexing (WDM). In this paper, we propose a WDM-based electronic–photonic switching network (EPSN) to realize the functions of the binary decoder and the multiplexer, which are fundamental elements in microprocessors for data transportation and processing. We experimentally demonstrate its practicality by implementing a 3–8 (three inputs, eight outputs) switching network operating at 20 Gb/s. Detailed performance analysis and performance enhancement techniques are also given in this paper.

scholarly journals Colloidal Quantum Dots and Metal Halide Perovskite Hybridization for Solar Cells Stability and Performance Enhancement

2021 ◽  
Author(s):  
Dong Yan ◽  
Mengxia Liu ◽  
Zhe Li ◽  
Bo Hou
Keyword(s):  
Quantum Dots ◽  
Solar Cells ◽  
High Performance ◽  
Performance Enhancement ◽  
Metal Halide ◽  
Colloidal Quantum Dots ◽  
Metal Halide Perovskite ◽  
Photoactive Materials ◽  
Halide Perovskites ◽  
And Performance

Metal halide perovskites and colloidal quantum dots (QDs) are two emerging class of photoactive materials that has been attracted considerable attention for next-generation high-performance solution-processed solar cells. In particular, the...

Performance of different hybrid dispersion compensation modules (DCMs) in long reach ultra dense WDM passive optical networks

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Shippu Sachdeva ◽  
Jagjit Malhotra ◽  
Manoj Kumar
Keyword(s):  
Optical Networks ◽  
Cost Reduction ◽  
High Performance ◽  
Performance Enhancement ◽  
Dispersion Compensation ◽  
Optical Network ◽  
Passive Optical Network ◽  
Dense Wdm ◽  
And Performance ◽  
Wdm Pon

Abstract Long reach Passive optical network (LR-PON) is an attractive solution to fulfill the ever-increasing bandwidth requirements due to propelling internet applications and competent to serve distant optical network units (ONUs). Wavelength division multiplexed (WDM) PON systems experience distance and performance limiting constraint termed as Dispersion. In order to compensate dispersion effects, Fiber bragg gratings (FBGs) and Dispersion compensation fibers (DCFs) are incorporated extensively in PONs. Performance of DCF is better than FBG in terms of dispersion compensation, but it comes at the cost of 3 $/m (very expensive). Therefore, long reach ultra dense WDM-PON systems are needed with incorporation of economical and high performance DCMs. Three newly constructed hybrid DCMs are investigated such as FBG-DCF (module 1), OPC-DCF (module 2), and FBG-DCF-OPC (module 3) in WDM-PON to get optimal DCM in terms of dispersion compensation efficiency (DCE) and economical operation. As per author’s best knowledge, DCE calculations and performance enhancement with cost reduction using hybrid DCMs in ultra dense WDM-PON, is not reported so far. WDM-PON consists of 32 channels at 25 GHz channel spacing is analyzed for 300 km link distance at 10 Gbps/channel using different hybrid DCMs. It is perceived that highest DCE of 70% is given by module 3 with maximum cost reduction of 19.84%. DCE performance of three modules is as follows: Module 3 (DCE 70%), Module 1 (DCE 55%), Module 2 (DCE 45%) and cost reduction/increase from conventional module by 19.84% reduction (Module 3), 19.05% reduction (Module 1), and increase 10.5% (Module 2). Hence, Module 3 is preferred for long reach WDM-PON to get high performance with lesser cost.

Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components

2021 ◽  
Vol 14 (3) ◽  
pp. 1-33
Author(s):  
Enrico Reggiani ◽  
Emanuele DEL Sozzo ◽  
Davide Conficconi ◽  
Giuseppe Natale ◽  
Carlo Moroni ◽  
...  
Keyword(s):  
Power Efficiency ◽  
High Performance ◽  
Performance Enhancement ◽  
State Of The Art ◽  
Design Flow ◽  
Art Works ◽  
Multiple Devices ◽  
High Performance Systems ◽  
Computationally Intensive ◽  
And Performance

Stencil-based algorithms are a relevant class of computational kernels in high-performance systems, as they appear in a plethora of fields, from image processing to seismic simulations, from numerical methods to physical modeling. Among the various incarnations of stencil-based computations, Iterative Stencil Loops (ISLs) and Convolutional Neural Networks (CNNs) represent two well-known examples of kernels belonging to the stencil class. Indeed, ISLs apply the same stencil several times until convergence, while CNN layers leverage stencils to extract features from an image. The computationally intensive essence of ISLs, CNNs, and in general stencil-based workloads, requires solutions able to produce efficient implementations in terms of throughput and power efficiency. In this context, FPGAs are ideal candidates for such workloads, as they allow design architectures tailored to the stencil regular computational pattern. Moreover, the ever-growing need for performance enhancement leads FPGA-based architectures to scale to multiple devices to benefit from a distributed acceleration. For this reason, we propose a library of HDL components to effectively compute ISLs and CNNs inference on FPGA, along with a scalable multi-FPGA architecture, based on custom PCB interconnects. Our solution eases the design flow and guarantees both scalability and performance competitive with state-of-the-art works.

Sign in / Sign up

Export Citation Format

Share Document