A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications

2009 ◽  
Author(s):  
Sungmin Bae ◽  
Krishnan Ramakrishnan ◽  
Narayanan Vijaykrishnan
Keyword(s):  
Low Power ◽  
Low Area ◽  
Fpga Architecture ◽  
Area Overhead ◽  
Body Bias

An Efficient FPGA Architecture with High-Performance 2D DWT Processor for Medical Imaging

2016 ◽  
Vol 25 (09) ◽  
pp. 1650110 ◽  
Author(s):  
S. P. Valan Arasu ◽  
S. Baulkani
Keyword(s):  
Medical Imaging ◽  
Low Power ◽  
Image Fusion ◽  
High Performance ◽  
Large Scale ◽  
Medical Images ◽  
Discrete Wavelet ◽  
Significant Information ◽  
Low Area ◽  
Fpga Architecture

Medical image fusion is the process of deriving vital information from multimodality medical images. Some important applications of image fusion are medical imaging, remote control sensing, personal computer vision and robotics. For medical diagnosis, computerized tomography (CT) gives the best information about denser tissue with a lesser amount of distortion and magnetic resonance image (MRI) gives the better information on soft tissue with little higher distortion. The main scheme is to combine CT and MRI images for getting most significant information. The need is to focus on less power consumption and less occupational area in the implementations of the applications involving image fusion using discrete wavelet transform (DWT). To design the DWT processor with low power and area, a low power multiplier and shifter are incorporated in the hardware. This low power DWT improves the spatial resolution of fused image and also preserve the color appearance. Also, the adaptation of the lifting scheme in the 2D DWT process further improves the power reduction. In order to implement this 2D DWT processor in field-programmable gate array (FPGA) architecture as a very large scale integration (VLSI)-based design, the process is simulated with Xilinx 14.1 tools and also using MATLAB. When comparing the performance of this low power DWT and other available methods, this high performance processor has 24%, 54% and 53% of improvements on the parameters like standard deviation (SD), root mean square error (RMSE) and entropy. Thus, we are obtaining a low power, low area and good performance FPGA architecture suited for VLSI, for extracting the needed information from multimodality medical images with image fusion.

scholarly journals A Kernel-Based Partitioning Algorithm for Low-Power, Low-Area Overhead Circuit Design Using Don’t-Care Sets

ETRI Journal ◽  
2016 ◽  
Author(s):  
Ick-Sung Choi ◽  
Hyoung Kim ◽  
Shin-Il Lim ◽  
Sun-Young Hwang ◽  
Bhum-Cheol Lee ◽  
...  
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Low Area ◽  
Area Overhead ◽  
Partitioning Algorithm

A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller

2021 ◽  
pp. 1-11
Author(s):  
Peng Yin ◽  
Zhou Shu ◽  
Yingjun Xia ◽  
Tianmei Shen ◽  
Xiao Guan ◽  
...  
Keyword(s):  
Low Power ◽  
Word Alignment ◽  
Low Area

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

An ultra-low-power CMOS voltage reference generator based on body bias technique

2013 ◽  
Vol 44 (12) ◽  
pp. 1145-1153 ◽  
Author(s):  
Yanhan Zeng ◽  
Yirong Huang ◽  
Yunling Luo ◽  
Hong-Zhou Tan
Keyword(s):  
Low Power ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Reference Generator ◽  
Low Power Cmos ◽  
Cmos Voltage Reference ◽  
Body Bias
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