Structural and Electrical Characteristics of Alternative High-k Dielectrics for CMOS Applications

High-k Gate Dielectrics for CMOS Technology ◽

10.1002/9783527646340.ch5 ◽

2012 ◽

pp. 111-184 ◽

Author(s):

Fu-Chien Chiu ◽

Somnath Mondal ◽

Tung-Ming Pan

Keyword(s):

Electrical Characteristics ◽

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Electrical Characteristics of Au/n-GaN Schottky Junction with a High-k SrTiO3 Insulating Layer

Journal of Nano- and Electronic Physics ◽

10.21272/jnep.11(4).04005 ◽

2019 ◽

Vol 11 (4) ◽

pp. 04005-1-04005-5 ◽

Author(s):

Varra Reddy ◽

◽

D. V. Vivekananda ◽

G. Sai Krishna ◽

B. Sri Vivek ◽

...

Keyword(s):

Schottky Junction ◽

Electrical Characteristics ◽

Insulating Layer ◽

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Impact of HfO2 buffer layer on the electrical characteristics of ferroelectric/high-k gate stack for nonvolatile memory applications

Applied Physics A ◽

10.1007/s00339-020-03632-0 ◽

2020 ◽

Vol 126 (6) ◽

Author(s):

Rajesh Kumar Jha ◽

Prashant Singh ◽

Upendra Kashniyal ◽

Manish Goswami ◽

B. R. Singh

Keyword(s):

Buffer Layer ◽

Nonvolatile Memory ◽

Electrical Characteristics ◽

High K ◽

Memory Applications

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Electrical characteristics of atomic layer deposited aluminium oxide and lanthanum-zirconium oxide high-k Dielectric stacks

2009 10th International Conference on Ultimate Integration of Silicon ◽

10.1109/ulis.2009.4897573 ◽

2009 ◽

Author(s):

S. Abermann ◽

C. Henkel ◽

O. Bethge ◽

E. Bertagnolli

Keyword(s):

Zirconium Oxide ◽

Aluminium Oxide ◽

Atomic Layer ◽

Electrical Characteristics ◽

High K ◽

High K Dielectric ◽

Lanthanum Zirconium Oxide

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Electrical Characteristics of SiO$_{2}$/High-k Dielectric Stacked Tunnel Barriers for Nonvolatile Memory Applications

Journal of the Korean Physical Society ◽

10.3938/jkps.55.116 ◽

2009 ◽

Vol 55 (1) ◽

pp. 116-119 ◽

Author(s):

Goon-Ho Park ◽

Kwan-Su Kim ◽

Myung-Ho Jung ◽

Won-Ju Cho ◽

Jongwan Jung

Keyword(s):

Nonvolatile Memory ◽

Electrical Characteristics ◽

High K ◽

Tunnel Barriers ◽

High K Dielectric ◽

Memory Applications

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Analysis of Al2O3 high-k gate dielectric effect on the electrical characteristics of a 4H-SiC low-power MOSFET

2019 1st International Conference on Sustainable Renewable Energy Systems and Applications (ICSRESA) ◽

10.1109/icsresa49121.2019.9182412 ◽

2019 ◽

Author(s):

Hichem Bencherif ◽

Abderrahim Yousfi ◽

Lakhdar Dehimi ◽

Fortunato Pezzimenti ◽

Francesco G. Della Corte

Keyword(s):

Low Power ◽

Gate Dielectric ◽

Electrical Characteristics ◽

Power Mosfet ◽

High K ◽

Dielectric Effect ◽

High K Gate Dielectric

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Impact of high-k gate dielectric with different angles of coverage on the electrical characteristics of gate-all-around field effect transistor: A simulation study

Results in Physics ◽

10.1016/j.rinp.2019.102823 ◽

2020 ◽

Vol 16 ◽

pp. 102823 ◽

Author(s):

Mohammad Karbalaei ◽

Daryoosh Dideban ◽

Hadi Heidari

Keyword(s):

Simulation Study ◽

Field Effect ◽

Field Effect Transistor ◽

Gate Dielectric ◽

Electrical Characteristics ◽

High K ◽

Effect Transistor ◽

High K Gate Dielectric

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Improved electrical characteristics of high-k gated MOSFETs with post-growth treatment on interfacial layer

Microelectronic Engineering ◽

10.1016/j.mee.2015.02.028 ◽

2015 ◽

Vol 138 ◽

pp. 81-85 ◽

Author(s):

Dun-Bao Ruan ◽

Kuei-Shu Chang-Liao ◽

Chen-Chien Li ◽

Chun-Chang Lu ◽

Yu-Liang Liao ◽

...

Keyword(s):

Interfacial Layer ◽

Electrical Characteristics ◽

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Structural properties and electrical characteristics of high-k Dy2O3 gate dielectrics

Applied Surface Science ◽

10.1016/j.apsusc.2010.11.144 ◽

2011 ◽

Vol 257 (9) ◽

pp. 3964-3968 ◽

Author(s):

Tung-Ming Pan ◽

Wei-Tsung Chang ◽

Fu-Chien Chiu

Keyword(s):

Structural Properties ◽

Gate Dielectrics ◽

Electrical Characteristics ◽

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Structural and Electrical Characteristics of High-k Sm[sub 2]TiO[sub 5] Gate Dielectrics

Electrochemical and Solid-State Letters ◽

10.1149/1.3111768 ◽

2009 ◽

Vol 12 (6) ◽

pp. G27 ◽

Author(s):

Tung-Ming Pan ◽

Li-Chen Yen ◽

Chun-Chin Huang ◽

Wu-Ching Lin

Keyword(s):

Gate Dielectrics ◽

Electrical Characteristics ◽

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Electrical Characteristics of Engineered ZrO2/SiO2 Tunnel Barrier with a High-k HfO2 Trapping Layer for Non-Volatile Memory

10.7567/ssdm.2009.p-4-2 ◽

2009 ◽

Author(s):

H. W. You ◽

G. H. Park ◽

J. W. Jung ◽

W. J. Cho

Keyword(s):

Tunnel Barrier ◽

Electrical Characteristics ◽

High K ◽

Non Volatile Memory ◽

Volatile Memory

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