Universal gates on garbled circuit construction

2019 ◽  
pp. e5236
Author(s):  
A. Anasuya Threse Innocent ◽  
Sangeeta K ◽  
G. Prakash
Keyword(s):  
Garbled Circuit ◽  
Universal Gates

Design of All Optical Universal Gates using 2-D Photonic Crystals

2021 ◽  
Author(s):  
Abyash Gautam ◽  
Anil Kumar Shukla
Keyword(s):  
Photonic Crystals ◽  
All Optical ◽  
Universal Gates

Quantum-Dot Cellular Automata-Based Encoder Circuit Using Layered Universal Gates

2021 ◽  
pp. 217-230
Author(s):  
Birinderjit Singh Kalyan ◽  
Balwinder Singh
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata ◽  
Universal Gates

Implementation of Universal Gates (NAND) Based on Nano-Magnetic Logic Using Multiferroics

2016 ◽  
Vol 5 (4) ◽  
pp. 505-509 ◽  
Author(s):  
Anup Sarkar ◽  
Pranab K. Dutta ◽  
Ankush Ghosh ◽  
Sudhabindu Ray ◽  
Subir K. Sarkar
Keyword(s):  
Universal Gates

Q2R+Q2R AS A UNIVERSAL BILLIARD

1992 ◽  
Vol 03 (02) ◽  
pp. 251-266 ◽  
Author(s):  
PATRICIO CORDERO ◽  
ERIC GOLES ◽  
GONZALO HERNANDEZ
Keyword(s):  
Energy Change ◽  
Navier Stokes ◽  
Local Energy ◽  
Local Rule ◽  
Energy Profiles ◽  
Dynamical Properties ◽  
Universal Gates

In this work we study the computing capabilities as well as some dynamical properties of an automaton called M4R. This automaton corresponds to the mixing of the energy profiles of two independent copies of the Q2R automaton with frustrations. We associate to each copy of a Q2R an equivalent automaton M2R, which, with the Margoluos neighborhood, exhibits the local changes of the Q2R energy.1 By doing so we generalize the dynamics by upgrading M2R according to four partitions of the lattice. This new dynamics — called M4R — is based on a local rule which corresponds to the local energy change of two independent copies of Q2R. The M4R model is reversible and conservative (magnetization is constant in time) and it has properties of a discrete billiard (as some of the hydrodynamics discrete versions of Navier-Stokes models). Moreover, this automaton has powerful computing capabilities. In fact, by using some special configurations of M4R, we exhibit universal gates and register that allow us to code any algorithm.

scholarly journals From two types of electrostatic position-dependent semiconductor qubits to quantum universal gates and hybrid semiconductor-superconducting quantum computer

2019 ◽  
Author(s):  
Krzysztof Pomorski ◽  
Panagiotis Giounanlis ◽  
Elena Blokhina ◽  
Dirk Leipold ◽  
Pawel Peczkowski ◽  
...  
Keyword(s):  
Quantum Computer ◽  
Universal Gates

scholarly journals Error Mitigation for Universal Gates on Encoded Qubits

2021 ◽  
Vol 127 (20) ◽  
Author(s):  
Christophe Piveteau ◽  
David Sutter ◽  
Sergey Bravyi ◽  
Jay M. Gambetta ◽  
Kristan Temme
Keyword(s):  
Error Mitigation ◽  
Universal Gates

scholarly journals Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology

2021 ◽  
Vol 12 ◽  
pp. 1-8
Author(s):  
Sujata A. A ◽  
Lalitha. Y. S
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Software Tool ◽  
Cmos Technology ◽  
Effective Control ◽  
Low Area ◽  
Area Reduction ◽  
And Performance ◽  
Artificial Neural Network Ann ◽  
Universal Gates

The recent technologies in VLSI Chips have grown in terms of scaling of transistor and device parameters but still, there is challenging task for controlling current between the source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip, through which current can be controlled effectively. This paper is to address the issues present in CMOS technology and majorly concentrated on the proposed 4-bit Nano processor using FinFET 32nm technology by using the Cadence Virtuoso software tool. In the proposed Nano processor, the first part is to design using 4bit ALU which includes all basic and universal gates, efficient and high-speed adder, multiplier, and multiplexer. The Carry Save Adder (CSA) and multiplier are the major subcomponents which can optimize the power consumption and area reduction. The second part of the proposed Nano processor is 4-bit 6T SRAM and Encoder and decoder and also Artificial Neural Network (ANN). All these subcomponents are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS, at the last chip-level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% optimization in power dissipation and 47% optimization in leakage current, 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses compressed subsequently respectively. The basic gates and universal gates, CSA, subtraction, and MUX are integrated for 4-bit ALU design, and its delay, power consumption, and area are 0.104nsec, 314.4uW, and 56.8usqm respectively

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