An input controlled leakage restrainer transistor‐based technique for leakage and short‐circuit power reduction of 1‐bit hybrid full adders

2021 ◽  
Author(s):  
Mohammad Moradinezhad Maryan ◽  
Majid Amini‐Valashani ◽  
Seyed Javad Azhari
Keyword(s):  
Short Circuit ◽  
Power Reduction ◽  
Circuit Power

scholarly journals Short-Circuit Power Reduction by Using High-Threshold Transistors

2012 ◽  
Vol 2 (1) ◽  
pp. 69-78 ◽  
Author(s):  
Arkadiy Morgenshtein
Keyword(s):  
Short Circuit ◽  
Power Reduction ◽  
High Threshold ◽  
Circuit Power

A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology

2021 ◽  
Author(s):  
Mohammad Moradinezhad Maryan ◽  
Majid Amini-Valashani ◽  
Seyed Javad Azhari
Keyword(s):  
Short Circuit ◽  
Logic Gates ◽  
Cmos Technology ◽  
Power Reduction ◽  
Static Logic ◽  
Circuit Power

Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic

2009 ◽  
Author(s):  
Tong Lin ◽  
Kwen-Siong Chong ◽  
Bah-Hwee Gwee ◽  
Joseph S. Chang
Keyword(s):  
Short Circuit ◽  
Power Reduction ◽  
Power Gating ◽  
Asynchronous Logic ◽  
Fine Grained ◽  
Circuit Power

scholarly journals Power Optimization of Delay Constrained Circuits

VLSI Design ◽  
2001 ◽  
Vol 12 (2) ◽  
pp. 125-138
Author(s):  
Anshuman Nayak ◽  
Malay Haldar ◽  
Prith Banerjee ◽  
Chunhong Chen ◽  
Majid Sarrafzadeh
Keyword(s):  
Power Dissipation ◽  
Short Circuit ◽  
Average Power ◽  
Accurate Estimate ◽  
Voltage Scaling ◽  
Power Reduction ◽  
Total Power ◽  
Gate Sizing ◽  
Dynamic Power ◽  
Circuit Power

We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS) techniques for power optimizations. We introduce a fast heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the load capacitance of the gates. Our results show that the combination of VS and GS perform better than the techniques applied in isolation. An average power reduction of 73% is obtained when decisions are taken assuming dynamic power only. In contrast, average power reduction is 77% when decisons include the short circuit power dissipation.

scholarly journals The effects of new 2030 scenario: reduction of short-circuit power and widening of voltage dips

2018 ◽  
Author(s):  
L. Michi ◽  
E.M. Carlini ◽  
L. Caciolli ◽  
D. Polinelli ◽  
P. Capurso ◽  
...  
Keyword(s):  
Short Circuit ◽  
Scenario Reduction ◽  
Voltage Dips ◽  
Circuit Power

Measuring of real value of short-circuit power in island operation condition

2015 ◽  
Author(s):  
Michal Kolcun ◽  
Martin Kanalik ◽  
Dusan Medved ◽  
Zsolt Conka
Keyword(s):  
Short Circuit ◽  
Operation Condition ◽  
Real Value ◽  
Circuit Power

Short-circuit power dissipation estimation for CMOS logic gates

1994 ◽  
Vol 41 (11) ◽  
pp. 762-765 ◽  
Author(s):  
S.R. Vemuru ◽  
N. Scheinberg
Keyword(s):  
Power Dissipation ◽  
Short Circuit ◽  
Logic Gates ◽  
Circuit Power
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