We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS)
techniques for power optimizations. We introduce a fast heuristic for choosing gates for
sizing and voltage scaling such that the total power is minimized under delay constraints.
We also use a more accurate estimate for determining the power dissipation of
the circuit by taking into account the short circuit power along with the dynamic power.
A better model of the short circuit power is used which takes into account the load
capacitance of the gates. Our results show that the combination of VS and GS perform
better than the techniques applied in isolation. An average power reduction of 73% is
obtained when decisions are taken assuming dynamic power only. In contrast, average
power reduction is 77% when decisons include the short circuit power dissipation.
Short-Circuit Power Reduction by Using High-Threshold Transistors
