A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology

2021 ◽  
Author(s):  
Mohammad Moradinezhad Maryan ◽  
Majid Amini-Valashani ◽  
Seyed Javad Azhari
Keyword(s):  
Short Circuit ◽  
Logic Gates ◽  
Cmos Technology ◽  
Power Reduction ◽  
Static Logic ◽  
Circuit Power

scholarly journals Power Optimization of Delay Constrained Circuits

VLSI Design ◽  
2001 ◽  
Vol 12 (2) ◽  
pp. 125-138
Author(s):  
Anshuman Nayak ◽  
Malay Haldar ◽  
Prith Banerjee ◽  
Chunhong Chen ◽  
Majid Sarrafzadeh
Keyword(s):  
Power Dissipation ◽  
Short Circuit ◽  
Average Power ◽  
Accurate Estimate ◽  
Voltage Scaling ◽  
Power Reduction ◽  
Total Power ◽  
Gate Sizing ◽  
Dynamic Power ◽  
Circuit Power

We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS) techniques for power optimizations. We introduce a fast heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the load capacitance of the gates. Our results show that the combination of VS and GS perform better than the techniques applied in isolation. An average power reduction of 73% is obtained when decisions are taken assuming dynamic power only. In contrast, average power reduction is 77% when decisons include the short circuit power dissipation.

scholarly journals On Mixed PTL/Static Logic for Low-power and High-speed Circuits

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 399-406 ◽  
Author(s):  
Geun Rae Cho ◽  
Tom Chen
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Logic Gates ◽  
Cmos Technology ◽  
Cmos Process ◽  
Test Cases ◽  
Static Structure ◽  
Average Delay ◽  
Power Delay Product ◽  
Static Logic

We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure that mixes conventional PTL structure with static logic gates can achieve better performance and lower power consumption compared to conventional PTL structure. The goal is to use the static gates to perform both logic functions as well as buffering. Our experimental results demonstrate that the proposed mixed PTL structure beats pure static structure and conventional PTL in 9 out of 15 test cases for either delay or power consumption or both in a 0.25 μm CMOS process. The average delay, power consumption, and power-delay product of the proposed structure for 15 test cases are 10% to 20% better of than the pure static implementations and up to 50% better than the conventional PTL implementations.

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