High-Speed Performance Evaluation of a Large-Scale Shared-Bus Digital System

2015 ◽  
Vol 98 (10) ◽  
pp. 57-66 ◽  
Author(s):  
MASAFUMI KONDO ◽  
TOMOYUKI YOKOGAWA ◽  
YOICHIRO SATO ◽  
KAZUTAMI ARIMOTO
2014 ◽  
Vol 134 (2) ◽  
pp. 312-319
Author(s):  
Masafumi Kondo ◽  
Tomoyuki Yokogawa ◽  
Yoichiro Sato ◽  
Kazutami Arimoto

2007 ◽  
Vol 08 (04) ◽  
pp. 321-336 ◽  
Author(s):  
HIROAKI ECHIGO ◽  
YOSHITAKA SHIBATA ◽  
KAZUO TAKAHATA

In this paper, a robust and large scale resident-oriented safety information system on the occurrence of the various disasters constructed over a nationwide high-speed network is introduced. The evacuated residents can register their safety information to the local safety information servers in the evacuation area whether they can safely evaluated or not using mobile PCs or terminals at the evacuation place or mobile terminals on the way of evacuation. All of the local information servers are connected each other by wireless network and the safety information can be sent an upper-layer database in the district area and finally integrated into a district safety information in that region. In our system some of the damaged local servers due to the disaster can be detected and recovered by the upper-layer database server. On the other hand, the upper-layer database servers are backed up by mirror servers located at mutually different locations with long distance to isolate the influence of the same disaster when the some of them were destroyed or disordered. Thus, by introducing two levels of redundancy and backup functions, more large scale and robust safety information database system can be realized. A prototype system is constructed over Japan Gigabit Network (JGN2) to evaluate the performance of the suggested system. Through the performance evaluation for the prototype system, we could verify the usability and scalability of our suggested system.


2004 ◽  
Vol 14 (03) ◽  
pp. 646-651 ◽  
Author(s):  
STEVEN EUGENE TURNER ◽  
DAVID E. KOTECKI

High-speed accumulators are frequently used as a benchmark of the high-speed performance and ability to yield large scale circuits in InP double hetereojunction bipolar (DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bit accumulator with 624 transistors operating at 41 GHz clock frequency with a power consumption of 4.1W. In this work, we report on modifications that allow the circuit to operate at a lower supply voltage and a corresponding lower power consumption. Simulation results for this modification indicate that a 16% power reduction can be obtained, while maintaining a high-speed operating frequency of 40 GHz.


Author(s):  
Gaurav Mattey ◽  
Lava Ranganathan

Abstract Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.


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