A new multipassband filter with multiple transmission zeros based on quarter-wavelength resonators in wireless communication systems

2015 ◽  
Vol 57 (5) ◽  
pp. 1105-1107
Author(s):  
Xin Cao ◽  
Zongxi Tang ◽  
Fei Wang ◽  
Yunqiu Wu ◽  
Biao Zhang
2021 ◽  
Vol 10 (1) ◽  
pp. 232-240
Author(s):  
Mussa Mabrok ◽  
Zahriladha Zakaria ◽  
Yully Erwanti Masrukin ◽  
Tole Sutikno ◽  
Hussein Alsariera

Due to the progression growth of multiservice wireless communication systems in a single device, multiband bandpass filter has attract a great attention to the end user. Therefore, multiband bandpass filter is a crucial component in the multiband transceivers systems which can support multiple services in one device. This paper presents a design of dual-band bandpass filter at 2.4 GHz and 3.5 GHz for WLAN and WiMAX applications. Firstly, the wideband bandpass filter is designed at a center frequency of 3 GHz based on quarter-wavelength short circuited stub. Three types of defected microstrip structure (DMS) are implemented to produce a wide notch band, which are T-inversed shape, C-shape, and U- Shape. Based on the performance comparisons, U-shaped DMS is selected to be integrated with the bandpass filter. The designed filter achieved two passbands centered at 2.51 GHz and 3.59 GHz with 3 dB bandwidth of 15.94 % and 15.86 %. The proposed design is very useful for wireless communication systems and its applications such as WLAN and WiMAX 


Author(s):  
A. Suresh Babu ◽  
B. Anand

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.


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