Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System

2005 ◽  
pp. 704-713 ◽  
Author(s):  
Howard Chen ◽  
Louis Hsu
Keyword(s):  
Monitoring System ◽  
Circuit Design ◽  
Power Supply ◽  
Power Supply Noise ◽  
Supply Noise ◽  
On Chip ◽  
Design Techniques

On-chip power supply noise and its implications on timing

2010 ◽  
Author(s):  
Lars J. Svensson ◽  
Johnny Pihl ◽  
Daniel A. Andersson ◽  
Per Larsson-Edefors
Keyword(s):  
Power Supply ◽  
Power Supply Noise ◽  
Supply Noise ◽  
On Chip

Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise

2010 ◽  
Vol 18 (1) ◽  
pp. 157-161 ◽  
Author(s):  
Eric Bohannon ◽  
Christopher Urban ◽  
Mark Pude ◽  
Yoshinori Nishi ◽  
Anand Gopalan ◽  
...  
Keyword(s):  
Power Supply ◽  
High Frequency ◽  
Power Supply Noise ◽  
Reduction Techniques ◽  
Supply Noise ◽  
On Chip

Research on Timing of on-Chip Power Supply Noise with Analysis of Scientific Data Materials

2013 ◽  
Vol 310 ◽  
pp. 494-497
Author(s):  
Xiao Guang Li
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Timing Analysis ◽  
Logic Gates ◽  
Scientific Data ◽  
New Method ◽  
Power Supply Noise ◽  
Supply Noise ◽  
On Chip

Aiming at the problems of the influence in power-supply variations on timing analysis, this paper presents a new method to assign a supply-dependent hold margin based on analysis of scientific data materials, which describe a method to accurately characterize logic gates for the sensitivity of delay on supply-voltage variations, and then the method use a commercial microcontroller as a design example. Experiment results shows that the new method with analysis of scientific materials can get a good performance, even under the existing noise.

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