Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS

Author(s):  
S. Govindarajan ◽  
R. Vemuri
Author(s):  
Anant Chawla ◽  
Joshua D. Summers

Morphological charts are widely recognized tools in engineering design applications and research. However, a literature gap exists in instructing the representation and exploration of morphological charts. In this paper, an experiment is conducted to understand how morphological charts are explored and what impact functional arrangement has on it. The experiment consisted of two problem statements, each with five different functional arrangements: 1) Most to Least Important Function, 2) Least to Most Important Function, 3) Input to Output Function, 4) Output to Input Function, and 5) Random. Sixty-seven junior mechanical engineering students were provided a prepopulated morphological chart and asked to generate integrated design concepts. The generated concepts were analyzed to determine how frequently a given means is selected, how much of the chart is explored, what is the sequence of exploration, and finally the influence of function ordering on them. Experimental results indicate a tendency to focus more on the initial columns of the chart irrespective of functional order. Moreover, the Most-to-Least-Important functional order results in higher chances and uniformity of design space exploration.


2014 ◽  
Vol 27 (2) ◽  
pp. 235-249 ◽  
Author(s):  
Anirban Sengupta ◽  
Reza Sedaghat ◽  
Vipul Mishra

Design space exploration is an indispensable segment of High Level Synthesis (HLS) design of hardware accelerators. This paper presents a novel technique for Area-Execution time tradeoff using residual load decoding heuristics in genetic algorithms (GA) for integrated design space exploration (DSE) of scheduling and allocation. This approach is also able to resolve issues encountered during DSE of data paths for hardware accelerators, such as accuracy of the solution found, as well as the total exploration time during the process. The integrated solution found by the proposed approach satisfies the user specified constraints of hardware area and total execution time (not just latency), while at the same time offers a twofold unified solution of chaining based schedule and allocation. The cost function proposed in the genetic algorithm approach takes into account the functional units, multiplexers and demultiplexers needed during implementation. The proposed exploration system (ExpSys) was tested on a large number of benchmarks drawn from the literature for assessment of its efficiency. Results indicate an average improvement in Quality of Results (QoR) greater than 26% when compared to a recent well known GA based exploration method.


2019 ◽  
Vol 141 (9) ◽  
Author(s):  
Anant Chawla ◽  
Joshua D. Summers

Although morphological charts are widely taught used tools in engineering design, little formal guidance is provided regarding their representation and exploration. Thus, an experiment was conducted to elucidate the influence of functional ordering on the exploration of morphological charts. Two design prompts were used, each with five different functional arrangements: (1) most-to-least important function, (2) least-to-most important function, (3) input-to-output function, (4) output-to-input function, and (5) Random. Sixty-seven junior mechanical engineering students were asked to generate integrated design concepts from prepopulated morphological charts for each design prompt. The concepts were analyzed to determine the frequency with which a given means was selected, how much of the chart was explored, the sequence of exploration, and the influence of function ordering. Results indicated a tendency to focus upon the initial columns of the chart irrespective of functional order. The most-to-least-important functional order resulted in higher chances and a uniformity of design space exploration.


2021 ◽  
Author(s):  
Michael Gebremariam

The objective of this project is to develop a software tool which assists in comparison of a work known as "M-GenESys: Multi Structure Genetic Algorithm based Design Space Exploration System for Integrated Scheduling, Allocation and Binding in High Level Synthesis" with another well established GA approach known as "A Generic Algorithm for the Design Space Exploration of Data paths During High-Level Synthesis". Two sets of software are developed based on both approaches using Microsoft Visual 2005 C# language. The C# language is an object-oriented language that is aimed at enabling programmers to quickly develop a wide range of applications on the Microsoft .NET platform. The goal of C# and the .NET platform is to shorten development time by freeing the developer from worrying about several low level plumbing issues such as memory equipment, type safety issues, building low level libraries, array bound checking, etc., thus allowing developers to actually spend their time and energy working on the application and business logic.


2019 ◽  
Vol 123 (1266) ◽  
pp. 1193-1215 ◽  
Author(s):  
N. H. Crisp ◽  
K. L. Smith ◽  
P. M. Hollingsworth

ABSTRACTA growing interest in constellations of small satellites has recently emerged due to the increasing capability of these platforms and their reduced time and cost of development. However, in the absence of dedicated launch services for these systems, alternative methods for the deployment of these constellations must be considered which can take advantage of the availability of secondary-payload launch opportunities. Furthermore, a means of exploring the effects and tradeoffs in corresponding system architectures is required. This paper presents a methodology to integrate the deployment of constellations of small satellites into the wider design process for these systems. Using a method of design-space exploration, enhanced understanding of the tradespace is supported , whilst identification of system designs for development is enabled by the application of an optimisation process. To demonstrate the method, a simplified analysis framework and a multiobjective genetic algorithm are implemented for three mission case-studies with differing application. The first two cases, modelled on existing constellations, indicate the benefits of design-space exploration, and possible savings which could be made in cost, system mass, or deployment time. The third case, based on a proposed Earth observation nanosatellite constellation, focuses on deployment following launch using a secondary-payload opportunity and demonstrates the breadth of feasible solutions which may not be considered if only point-designs are generated by a priori analysis. These results indicate that the presented method can support the development of future constellations of small satellites by improving the knowledge of different deployment strategies available during the early design phases and through enhanced exploration and identification of promising design alternatives.


2007 ◽  
Vol 2 (1) ◽  
pp. 45-54
Author(s):  
Paulo Sérgio Brandão Do Nascimento ◽  
Stelita M. Da Silva ◽  
Jordana L. Seixas ◽  
Remy E. Sant’Anna ◽  
Manoel E. De Lima

High parallelism degree is fundamental for high speed massive data processing systems. Modern FPGA devices can provide such parallelism plus flexibility. However, these devices are still limited by their logic block size, memory size, memory bandwidth and configuration time. Temporal partitioning techniques can be a solution for such problems when FPGAs are used to implement large systems. In this case, the system is split into partitions (called contexts), multiplexed in a FPGA, by using reconfiguration techniques. This approach can increase the effective area for system implementation, allowing increase of parallelism in each task that composes the application. However, the necessary reconfiguration time between contexts can cause performance decrease. A possible solution for this is an intensive parallelism exploration of massive data application to compensate for this overhead and improve global performance. This is true for modern FPGA with relatively high reconfiguration speed. In this work, A reconfigurable computer platform and design space exploration techniques are proposed for mapping of such massive data applications, as image processing, in FPGA devices, depending on the application task scheduling. A library with different hardware implementation for a different parallelism degree is used for better adjustment of space/time for each task. Experiments demonstrate the efficiency of this approach when compared to the optimal mapping reached by exhaustive timing search in the complete design space exploration. A design flow is shown based on library components that implements typical tasks used in the domain of applications.


2021 ◽  
Author(s):  
Michael Gebremariam

The objective of this project is to develop a software tool which assists in comparison of a work known as "M-GenESys: Multi Structure Genetic Algorithm based Design Space Exploration System for Integrated Scheduling, Allocation and Binding in High Level Synthesis" with another well established GA approach known as "A Generic Algorithm for the Design Space Exploration of Data paths During High-Level Synthesis". Two sets of software are developed based on both approaches using Microsoft Visual 2005 C# language. The C# language is an object-oriented language that is aimed at enabling programmers to quickly develop a wide range of applications on the Microsoft .NET platform. The goal of C# and the .NET platform is to shorten development time by freeing the developer from worrying about several low level plumbing issues such as memory equipment, type safety issues, building low level libraries, array bound checking, etc., thus allowing developers to actually spend their time and energy working on the application and business logic.


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