SIMD (Single Instruction Multiple Data Processing)

2008 ◽  
pp. 817-819 ◽  
Keyword(s):  
Data Processing ◽  
Single Instruction Multiple Data ◽  
Multiple Data

An Implementation of Configurable SIMD Core on FPGA

2013 ◽  
Vol 336-338 ◽  
pp. 1925-1929
Author(s):  
Guang Wang ◽  
Yin Sheng Gao
Keyword(s):  
Wireless Communications ◽  
Data Processing ◽  
Single Instruction Multiple Data ◽  
Instruction Set ◽  
Instruction Set Architecture ◽  
Multiple Data ◽  
4G Wireless ◽  
Main Components ◽  
Computing Speed

In order to meet the computing speed required by 4G wireless communications, and to provide the different data processing widths required by different algorithms, an SIMD (Single Instruction Multiple Data) core has been designed. The ISA (Instruction Set Architecture) and main components of the SIMD core are discussed focus on how the SIMD core can be configured. Finally, the simulation result of the multiplication of two 8*8 matrices is presented to show the execution of instructions in the proposed SIMD core, and the result verifies the correctness of the SIMD core design.

An Efficient Implementation of Semi-numerical Computation of the Hartree-Fock Exchange Matrix on the Intel Phi Processor

2017 ◽  
Author(s):  
fenglai liu ◽  
Jing Kong
Keyword(s):  
Data Processing ◽  
Numerical Computation ◽  
Basis Set ◽  
Single Instruction Multiple Data ◽  
Processing Unit ◽  
Efficient Utilization ◽  
Data Processing Unit ◽  
Hartree Fock ◽  
Multiple Data ◽  
Exchange Matrix

In this work we present an efficient semi-numerical integral implementation specially designed for the Intel Phi processor to calculate the Hartree-Fock exchange matrix and the energy. Compared with the implementation for the CPU platform, to achieve a productive implementation one needs to focus on the efficient utilization of the SIMD(Single instruction, multiple data) processing unit and maximum cache usage in the Phi processor. For evaluating the efficiency of the implementation, we performed benchmark calculations on the buckyball molecules C60, C100, C180 and C240. For the calculations with basis set 6-311G(2df) and cc-pvtz the benchmark test shows 7-12 times of speedup on the Knight Landing Phi processor 7250 in comparison with traditional four-center electron repulsion integral calculation performed on a six-core Xeon E5-1650 CPU.<br>

scholarly journals abPOA: an SIMD-based C library for fast partial order alignment using adaptive band

2020 ◽  
Author(s):  
Yan Gao ◽  
Yongzhuang Liu ◽  
Yanmei Ma ◽  
Bo Liu ◽  
Yadong Wang ◽  
...  
Keyword(s):  
Error Correction ◽  
Partial Order ◽  
Directed Acyclic Graph ◽  
State Of The Art ◽  
Single Instruction Multiple Data ◽  
Multiple Sequence ◽  
Software Interface ◽  
Multiple Data ◽  
Long Read ◽  
Read Error Correction

AbstractSummaryPartial order alignment, which aligns a sequence to a directed acyclic graph, is now frequently used as a key component in long-read error correction and assembly. We present abPOA (adaptive banded Partial Order Alignment), a Single Instruction Multiple Data (SIMD) based C library for fast partial order alignment using adaptive banded dynamic programming. It can work as a stand-alone multiple sequence alignment and consensus calling tool or be easily integrated into any long-read error correction and assembly workflow. Compared to a state-of-the-art tool (SPOA), abPOA is up to 15 times faster with a comparable alignment accuracy.Availability and implementationabPOA is implemented in C. A stand-alone tool and a C/Python software interface are freely available at https://github.com/yangao07/[email protected] or [email protected]

SIMD (Single Instruction, Multiple Data) Machines

2011 ◽  
pp. 1819-1819
Author(s):  
Jack Dongarra ◽  
Piotr Luszczek ◽  
Felix Wolf ◽  
Jesper Larsson Träff ◽  
Patrice Quinton ◽  
...  
Keyword(s):  
Single Instruction Multiple Data ◽  
Multiple Data

scholarly journals A scalable ASIP for BP Polar decoding with multiple code lengths

2018 ◽  
Vol 232 ◽  
pp. 01046
Author(s):  
Wan Qiao ◽  
Dake Liu
Keyword(s):  
Cmos Technology ◽  
Single Instruction Multiple Data ◽  
Instruction Set ◽  
Maximum Throughput ◽  
Specific Instruction ◽  
Area Efficiency ◽  
Multiple Data ◽  
High Area ◽  
Multiple Code ◽  
Application Specific

In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with state-of-art Polar decoders reveals PASIP’s high area efficiency.

scholarly journals A Video Specific Instruction Set Architecture for ASIP design

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-7 ◽  
Author(s):  
Zheng Shen ◽  
Hu He ◽  
Yanjun Zhang ◽  
Yihe Sun
Keyword(s):  
Video Coding ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Single Instruction Multiple Data ◽  
Instruction Set ◽  
Instruction Set Architecture ◽  
Specific Instruction ◽  
Multiple Data ◽  
Signal Processors

This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.

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