A Novel Design Augmentation of Bio-Inspired Artificial Immune Technique in Securing Internet of Things (IOT)

Author(s):  
G. Usha ◽  
P. Madhavan ◽  
M. V. Ranjith Kumar
2020 ◽  
Vol 18 (1) ◽  
pp. 31-38
Author(s):  
Vivek Pogra ◽  
Santosh Kumar Vishvakarma ◽  
Balwinder Raj

This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the Internet. The transfer of data between different networks and internet of things (IoT) platform is controlled by IoT platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to the fact that it is designed for IoT applications. It is described in VHDL at RTL level and simulation is done on the Vivado 2016.2.


2011 ◽  
Vol 403-408 ◽  
pp. 2457-2460 ◽  
Author(s):  
Run Chen ◽  
Cai Ming Liu ◽  
Lu Xin Xiao

Grasping security situation of the Internet of Things (IoT) is useful to work out a scientific and reasonable strategy to defend the IoT security. In the interest of resolving the problems of the security situation sense technology for IoT, a security situation sense model based on artificial immune system for IoT is proposed in this paper. Security threat sense sub-model, formulation mechanism for security threat intensity and security situation assessment sub-model are established. The security threats in the IoT environment are surveyed effectively. Quantitative and accurate assessment for the Real-Time security situation is realized. Theoretical analysis shows that the proposed model is significative of theory and practice.


2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Congsi Wang ◽  
Shuai Yuan ◽  
Xiaodong Yang ◽  
Wei Gao ◽  
Cheng Zhu ◽  
...  

The position error of array antenna significantly deteriorates the gain and sidelobe of the array, which seriously hinders the realization of high performance of communication antenna for Internet of Things (IoT). Based on the sensitivity analysis theory, the sensitivity of the array radiation field with respect to the position of the antenna element is derived. Besides, a novel design method of position tolerance for array antenna is proposed and applied to a 20×20 planar array. Compared with the array designed by traditional method, the gain loss is basically the same (being 0.5 dB), while the peak sidelobe level is lowered by 1.937 dB (φ=0°)/1.586 dB (φ=90°). Besides, the uncertainty analysis results show that the newly designed array has a much higher chance to achieve the desired performance, which fully demonstrates the innovation and effectiveness of the new method.


2020 ◽  
Vol 18 (9) ◽  
pp. 700-705
Author(s):  
Vivek Pogra ◽  
Amandeep Singh ◽  
Santosh Kumar Vishvakarma ◽  
Balwinder Raj

This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.


IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 136186-136197
Author(s):  
Xuyang Ding ◽  
Ying Xie ◽  
Pengxiao Li ◽  
Mengtian Cui ◽  
Jianying Chen

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